NCSU Institutional Repository >
NC State Theses and Dissertations >
Theses >

Please use this identifier to cite or link to this item: http://www.lib.ncsu.edu/resolver/1840.16/186

Title: High-Speed Transceiver Design in CMOS using Multi-level (4-PAM) Signaling
Authors: Joseph, Balu
Advisors: Dr. Gianluca Lazzi, Committee Member
Dr. Wentai Liu, Committee Chair
Dr. Rhett Davis, Committee Member
Keywords: high-speed transceiver
equalization
CDR
serial-link
SERDES
multi-level
4-PAM
Issue Date: 22-Apr-2003
Degree: MS
Discipline: Electrical Engineering
Abstract: The design of a 4 Gbps serial link transceiver in 0.35μm CMOS process is presented. The major factors limiting the performance of high-speed links are transmission channel bandwidth, timing uncertainty and on-chip frequency limitations. The design uses a combination of multi-level signaling (4-PAM) and transmit pre-emphasis to overcome the channel low-pass characteristics. High on-chip frequency signals are avoided by multiplexing and de-multiplexing the data directly at the pads. Timing recovery is done through over-sampling the data using multi-phase clocks generated from a low-jitter PLL. The design achieves a 4 Gbps data transmission rate, with a transmit data jitter of 53.2 ps (p-p), while consuming 879.4 mW of power from a 3.3 V supply.
URI: http://www.lib.ncsu.edu/resolver/1840.16/186
Appears in Collections:Theses

Files in This Item:

File Description SizeFormat
etd.pdf5.26 MBAdobe PDFView/Open

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.