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Please use this identifier to cite or link to this item: http://www.lib.ncsu.edu/resolver/1840.16/2037

Title: STI Concepts for Bit-Bang Communication Protocols
Authors: Kumar, Nagendra J
Advisors: Dr. Thomas M. Conte, Committee Member
Dr. Eric Rotenberg, Committee Member
Dr. Alexander Dean, Committee Chair
Keywords: STI
J1850
Issue Date: 28-Jan-2003
Degree: MS
Discipline: Computer Engineering
Abstract: In the modern times, embedded communication networks are being used in increased number of embedded systems to provide more reliability and cost effectiveness. Designers are forced to limit and minimize the size, weight, power consumption, costs and also the design time of their products. However, network controller chips are also expensive and hence moving functionality from hardware to software cuts down the costs and also makes custom fit protocols easier to implement. Traditional methods of sharing a processor are not adequate for implementing communication protocol controllers in software because of the processing required during each bit. The available idle time is fine grain compared to the bit time and is usually small for even the fast context switching techniques (e.g. co-routines) to run any other thread. Without some scheme to recover this fine-grain idle time, no other work in the system would make any progress. Software Thread Integration (STI) provides low cost concurrency on general-purpose microprocessors by interleaving multiple threads of control (having real-time constraints) into one. This thesis introduces new methods for implementing communication protocols in software using statically scheduled co-routines and software thread integration. With co-routines, switching from primary to secondary threads and vice versa can be done without incurring a penalty as severe as "context - switching". This technique will be been demonstrated on the SAE J1850 communication standard used in off- and on-road land-based vehicles. These methods also minimize the number of co-routine calls needed to share the processor thereby enabling finer-grain idle time to be recovered for use by the secondary thread. Increased number of compute cycles implies ∗Improved performance of the secondary thread and ∗Reduced minimum clock speed for the microprocessor. Thus, now more secondary thread work can be done and also the minimum clock speed required of the processor is reduced. These factors enable the embedded system designers to use processors more efficiently and also with less development effort.
URI: http://www.lib.ncsu.edu/resolver/1840.16/2037
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