NCSU Institutional Repository >
NC State Theses and Dissertations >
Theses >

Please use this identifier to cite or link to this item: http://www.lib.ncsu.edu/resolver/1840.16/2807

Title: Functional Verification of an ALU Core applying the Constrained Random approach
Authors: Hamilton, Patrick
Advisors: Dr.Eric Rotenberg, Committee Member
Dr.Rhett Davis, Committee Member
Dr. Paul Franzon, Committee Chair
Keywords: Bugs
Testplan
Escape Analysis
Regression
Reference model
Golden vectors
Patrick Hamilton
Functional Coverage
Code Coverage
Assertions
Testbench
Testcase
Functional Verification
Issue Date: 4-Jun-2003
Degree: MS
Discipline: Computer Engineering
Abstract: ASIC complexity is increasing so rapidly that designer productivity is not coping with the growth. Verification presents about 60-70% of the total design effort and only advances in verification methodology can improve the time to market considerably. Directed tests and 'golden' reference files will soon become the primitive tools of the modern test environment. Verification engineers are consequently looking towards new methodologies like Constrained-Random approach to reduce test bench development time, and speed-up the time it takes to achieve complete verification of their ASIC or SoC. Test bench automation tools for constrained-random stimulus generation and functional coverage create tests for corner cases that even engineers who designed the system may not anticipate and hence find bugs early in the development cycle. This thesis describes the study and implementation of the Constrained-Random concept in the Functional verification of a 32-bit ALU core using Specman.
URI: http://www.lib.ncsu.edu/resolver/1840.16/2807
Appears in Collections:Theses

Files in This Item:

File Description SizeFormat
etd.pdf3.87 MBAdobe PDFView/Open

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.