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Title: Study of Si1-xGex Junction Formation for SOI Based CMOS Technology
Authors: Du, Yan
Advisors: Dr. Mehmet C Ozturk, Committee Co-Chair
Dr. Veena Misra, Committee Chair
Dr. Carlton Osburn, Committee Member
Dr. Gerd Duscher, Committee Member
Keywords: nanowire
Issue Date: 8-Jan-2009
Degree: PhD
Discipline: Electrical Engineering
Abstract: SiGe source/drain technology has been sucessfully applied to bulk metal oxide semiconductor field effect transistors (MOSFETs). Both channel mobility and source/drain contact resistivity are substantially improved with this technology. In this dissertation, SiGe junction formation for silicon on insulator (SOI) based CMOS technology was investigated. Strain in epitaxially grown films on SOI films and silicon nanowires is studied using Raman spectroscopy and transmission electron microscope (TEM). For epitaxially grown SiGe film on SOI, there is lower degree of strain development in the SOI layer due to the rigid interface between the SOI and the burried oxide as compared to bulk. However, for silicon nanowires on oxide, the situation is different since nanowires serve as compliant substrates. Part of the strain energy is transferred to silicon nanowires. The consistency between synthesized Raman peak shifts and the experimental measurements verified the strain sharing between the epitaxially grown SiGe films and the silicon nanowires. Splittings of high order Laue zone line (HOLZ) from a convergent beam electron diffraction (CBED) pattern was quantified to study the strain distribution in epitaxial SiGe films grown on silicon nanowires. It was found out in this study that elastic deformation of epitaxial SiGe at free surfaces leads to strain relaxation at these surfaces. This phenomenon is detrimental to strain engineering in a nanowire MOSFET and provides new challenges to develop smart designs for constraining strain in the nano-structures. Moreover, atomic layer deposition (ALD) Platinum is proposed for metal deposition on 3D epitaxial SiGe source/drain. The uniform deposition around 3D SiGe films effectively increases the contact surface area which is highly desired in the FinFET application.
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