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Title: A Feasibility Study of an Asymmetric Dual Pipeline Processor Architecture
Authors: Rajagopal, Arianathan
Advisors: Prof. Eric Rotenberg, Committee Member
Prof. Yan Solihin, Committee Chair
Prof. Greg Byrd, Committee Member
Keywords: cluster predictor
asymmetric architecture
dual pipeline
Issue Date: 12-Aug-2003
Degree: MS
Discipline: Computer Engineering
Abstract: In modern deep pipeline processors, one of the major performance bottlenecks is branch misprediction. If the current trend towards deeper and wider pipelines continues, branch mispredictions will continue to be a challenge in microarchitecture design. Whereas a wide and deep pipeline provides high Instruction Level Parallelism in the absence of branch mispredictions, it becomes a cause for performance degradation for mispredicted branches. A shorter and narrower pipeline can reduce the branch misprediction penalty by reducing the branch resolution loop length, but does not provide high throughput when there are few mispredictions. This work proposes and evaluates the feasibility of a new architecture that tries to combine the advantages of both the deep pipeline and the short pipeline by making use of a dual pipeline architecture. We observe that branch mispredictions are often clustered. When there are few mispredictions, the deep pipeline is used to get a high throughput. When the mispredictions are clustered, i.e. they are separated by fewer number of instructions, the short pipeline is used. The control keeps transferring between the deep and short pipelines. A control mechanism between the two pipelines is needed to switch at the optimal time. The optimal time for switching to the short pipeline is at the start of clustered mispredictions, and the optimal time for switching back to the deep pipeline is at the end of clustered mispredictions. We present a Cluster Predictor and evaluate the proposed asymmetric architecture for a number of different configurations and benchmark applications.
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