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|Title: ||Breakdown and Reliability of CMOS Devices with Stacked Oxide/Nitride and Oxynitride Gate Dielectrics Prepared by RPECVD|
|Authors: ||Lee, Yi-Mu|
|Advisors: ||Carlton Osburn, Committee Co-Chair|
Gerald Lucovsky, Committee Co-Chair
John Hauser, Committee Member
Veena Misra, Committee Member
|Issue Date: ||9-Jun-2003|
|Discipline: ||Electrical Engineering|
|Abstract: ||Remote-plasma-enhanced CVD (RPECVD) silicon nitride and silicon oxynitride alloys have been proposed to be the attractive alternatives to replace conventional oxides as the CMOS logic and memory technology node is scaled beyond 100 nm. This dissertation is focused on the degradation and breakdown of RPECVD stacked oxide/nitride (O/N) and oxynitride gate dielectrics under constant-current stress (CCS) and constant-voltage stress (CVS). By monitoring the time-to-breakdown of the dielectrics, the device reliability can be determined and further used to evaluate the dielectric quality and the scaling limits of the dielectric thickness.
It is found that the breakdown behavior of the gate oxide and RPECVD gate dielectrics is influenced by the degree of boron penetration, which in turn leads to increases in the gate leakage current. During electrical stresses, positive charges and hole trapping are generated at the Si/SiO2 interface and also in the dielectric layer, resulting in device degradation and final breakdown. We successfully use the RPECVD technique to incorporate an ultrathin (~0.6 nm) interfacial oxide layer and one monolayer of nitrogen in the gate stacks to improve the interface properties. Therefore, the stress-induced charges and trapping are suppressed and the device performance including SILC, threshold voltage instability, drive current and switching characteristics is improved. In addition, shorter-channel devices show more degraded electrical properties compared to longer-channel devices due to the increased damaged region in the gate-drain overlap near the channel.
The TDDB reliability and lifetime of MOS devices with RPECVD O/N gate dielectric for the foreseeable mobile application are also investigated. This study is the first to reveal the trend of Weibull slopes and activation energy of O/N gate stacks. It has been found that Poisson area scaling is valid for O/N gate stack, indicating that the intrinsic breakdown is a random process and can be explained by the percolation model. Also, the voltage and temperature acceleration parameters are determined from TDDB. The projection of device lifetime based on total chip area and low percentile failure rate is demonstrated. The maximum tolerable operating voltage for a total gate area of 0.1 cm2 and 0.01% failure rate at 125° C is projected to be 1.9 V for 2.07 nm stacked O/N gate dielectrics.|
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