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|Title: ||A Methodology for Mapping Networking Applications to Multiprocessor-FPGA Configurable Computing Systems|
|Authors: ||Subramanian, Sivaramakrishnan|
|Advisors: ||Douglas S. Reeves, Committee Member|
Winser E. Alexander, Committee Co-Chair
Clay S. Gloster, Jr., Committee Co-Chair
Paul D. Franzon, Committee Member
|Issue Date: ||20-Jul-2003|
|Discipline: ||Computer Engineering|
|Abstract: ||Configurable Computing (CC) systems use Field Programmable Gate Arrays (FPGAs) to accelerate compute-intensive applications on general purpose processors. Networking applications are typically compute-intensive and require low initiation intervals in addition to small execution times. Network Processing Units (NPU) are integrated multiprocessors that have been optimized for networking applications. Due to their simplified bit-oriented architecture, NPUs exhibit reduced performance when applications require increased processing power per packet. Line-rate processing of complex-operation networking applications such as load-balancing, compression, application firewalls, or intrusion-detection requires a different approach to meet their high performance constraints. These applications can benefit from a methodology that combines the benefits of configurable computing with the multiprocessor features of network processors.
Until recently, solutions using multiple processors and FPGA devices were impractical in terms of power, area, cost and development time. Recent advances in Very Large Scale Integration (VLSI) technology have resulted in new high-density FPGA architectures with multiple embedded processors. Such highly integrated architectures enable practical solutions for line-rate processing of complex networking applications.
Existing methods of mapping applications to configurable computing systems are limited to architectures with a single general purpose processor and conventional FPGAs. Very little research has been published that addresses mapping of networking applications to multiprocessor FPGA systems. This thesis addresses this problem by proposing a methodology for mapping networking applications to multiprocessor-embedded FPGA systems. It presents an innovative architecture that uses multiprocessor pipelining and interleaving concepts along with configurable computing concepts to create a Configurable Application Pipeline (CAP). CAPillary, an algorithm for generating CAP solutions for a given networking application, is presented along with examples that demonstrate the effectiveness of the proposed methodology.|
|Appears in Collections:||Dissertations|
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