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Title: Planar Edge Defined Alternate Layer Process (PEDAL) - An Unconventional Technique for Fabricatinon of Wafer Scale Sub-25 nm Nanowires and Nanowire Template
Authors: Sonkusale, Sachin Ramrao
Advisors: Dr. Mark Johnson, Committee Member
Dr. Veena Misra, Committee Member
Dr. Gerald Iafrate, Committee Member
Dr. Paul D. Franzon, Committee Chair
Keywords: template
Issue Date: 8-Dec-2006
Degree: PhD
Discipline: Electrical Engineering
Abstract: As defined by the US national science foundation, "nanofabrication is the process of making functional structures with arbitrary patterns having minimum dimensions less than 100 nm". Nanofabrication, a key step in nanotechnology, has applications not only in conventional semiconductor devices but also in sensors, memory, nanofluidics, cross-bar logic architecture and nanoelectrical mechanical systems. In this research I have proposed and successfully demonstrated an unconventional lithographic technique called Planar Edge Defined Alternate Layer (PEDAL) to fabricate wafer scale sub 25 nm nanowire template. Good dimensional control and wafer scale uniformity of this process is shown by uniformity analysis of the width and spacing of an array of sixteen line-width structures with approximately 42 nm pitch and twenty four line-width structures with approximately 23 nm pitch. Results on routing capability of this process along with results of palladium nanowires obtained by PEDAL lift-off process done on the template with 42 nm pitch is also reported. In the case of template with array of sixteen lines, the average pitch of array across the 4 inch wafer was measured to be 40.83 nm with the standard deviation of 2.29 nm where as the average pitch of the lines in an array was found to be 41.5 nm with the standard deviation of 4.64 nm. After Pd lift-off the average pitch in nanowire array was measured to be 41.88 nm with standard deviation of 1.83 nm, close to the values obtained for the template. In the case of array of twenty four line-widths, average pitch of array across the 4 inch wafer was measured to be 21.1 nm with the standard deviation of 5 A where as the average pitch of the line in an array was found to be 22.6 nm with the standard deviation of 9 A. Other than experimental analysis, results from numerical simulations to find processing conditions to get good dimensional control in PEDAL process by taking process variations into account are also presented in this thesis.
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