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Please use this identifier to cite or link to this item: http://www.lib.ncsu.edu/resolver/1840.16/3861

Title: Controller in Core: An Adaptive Microarchitectural Model for System-level Optimization
Authors: Gao, Fei
Advisors: Suleyman Sair, Committee Chair
Thomas M Conte, Committee Member
Yan Solihin, Committee Member
Vincent Freeh, Committee Member
Keywords: performance bottleneck
program phase
value prediction
adaptive microarchitecture
Issue Date: 19-Jul-2007
Degree: PhD
Discipline: Electrical Engineering
Abstract: Modern processors are utilizing more complex microarchitectures to extract more Instruction Level Parallelism (ILP) ⁄ Thread Level Parallelism (TLP) to improve performance. In addition to performance concerns, power and thermal issues have also become important for microprocessor designers because of the increasing power/heat density and resulting cooling costs. Meanwhile, many runtime architectural optimization approaches, called adaptive microarchitectures, are proposed to optimize system resources dynamically based on the characteristics of applications. However, most of them focus on improving a specific microarchitecture component or metric. In this dissertation, we argue that system-wide optimization is the future of adaptive microarchitectures that can balance the tradeoffs between different optimization choices to achieve maximum overall performance. We propose a runtime optimization architectural model - Controller in Core (CiC), which uses a dedicated element to synthesize and analyze the system-wide runtime information and make judicious optimization decisions. To demonstrate the CiC model, we present a performance-oriented adaptive microarchitecture - an adaptive value predictor that tailors its value prediction functionality based on runtime system performance bottleneck analysis. We propose an event counter based performance model that can accurately estimate the performance cost for critical system events. Based on this model, we propose the bottleneck vector as the basis of long-term performance bottleneck analysis and a runtime bottleneck phase tracking scheme. In addition, three bottleneck phase prediction schemes are studied. Based on performance bottleneck analysis, we develop adaptation algorithms to control the adaptation of the adaptive value predictor. Our results show that the adaptive value predictor achieves 30% and 10% average performance gains when compared to the baseline and the traditional value predictor designs respectively.
URI: http://www.lib.ncsu.edu/resolver/1840.16/3861
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