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Please use this identifier to cite or link to this item: http://www.lib.ncsu.edu/resolver/1840.16/3990

Title: Active Body Bias for Low-Power Silicon-On-Insulator Design
Authors: Damiano, John
Advisors: W. Rhett Davis, Committee Member
Antonio Montalvo, Committee Member
Brian Hughes, Committee Member
Paul Franzon, Committee Chair
Angus Kingon, Committee Member
Keywords: SOI
circuit design
silicon-on-insulator
body bias
layout techniques
layout
Issue Date: 18-Apr-2007
Degree: PhD
Discipline: Electrical Engineering
Abstract: SOI device technology offers the circuit designer higher performance and greater flexibility. This work proposes the use of a targeted substrate bias and innovative device and circuit topologies to achieve higher performance and lower power while providing a strategy to compensate for wide temperature and process variations. This project introduces and evaluates a modified H-gate device topology (integrated drain-body transistor, or IDBT) vs. alternative structures using simulation supported by electrical results obtained from test circuits. The IDBT can be used to locally and dynamically reduce MOSFET VTH, increase switching speed, and improve circuit energy-delay product by up to 30%. For all structures investigated, the dynamic body bias provided by IDBTs provides improved logic cell performance vs. conventional source-tied cell designs. This work also examines use of body bias to compensate for temperature or process variations. The temperature range seen by space electronics exceeds standard commercial specs and even military specs. Integrated circuits placed on a satellite or lander vehicle may be expected to operate from below -200°C to over 200°C. In this environment, the stabilization of key circuit parameters across temperature, whether power consumption or performance metrics, can be accomplished through a targeted substrate bias. The amount of stabilization available, i.e. the degree to which key parameters can be shifted in-situ, is explored. Similarly, variations in device parameters due to process variations can also be compensated using this technique. Finally, these efforts exposed marginalities in the models for Honeywell MOI5 MOSFETs. At low temperatures, the simulated device characteristics diverged substantially from the electrical data, while the PMOS device simulation results displayed incorrect body factor. This work interprets these results and develops improved models based on electrical results from a series of test structures.
URI: http://www.lib.ncsu.edu/resolver/1840.16/3990
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