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|Title: ||Modeling and Design of a Transient Voltage Clamp Assisted Voltage Regulator|
|Authors: ||Li, Ding|
|Advisors: ||Alex Q. Huang, Committee Chair|
Kevin Gard, Committee Member
Subhashish Bhattacharya, Committee Member
|Keywords: ||load transient|
transient voltage clamp
|Issue Date: ||18-May-2007|
|Discipline: ||Electrical Engineering|
|Abstract: ||New power management techniques for microprocessor have been introduced as well as the CPU technology itself advanced. One solution is to decrease the power supply voltage such that total power loss is reduced. From the introduction of Intel Pentium processor, a non-standard supply voltage which is less than 5V was adopted. From then on, CPU supply voltage keeps decreasing. On the other hand, the increasing transistors count in microprocessor demands a continuously increase of microprocessor's current.
The fundamental requirements for Voltage Regulators (VR) are: (1) small voltage deviation during fast dynamic transients from light load to heavy load and vice-versa. This requirement becomes tighter when supply voltage goes below 1V. (2) High power density due to the limited motherboard space. (3) High conversion efficiency (low power loss) because of the thermal management capability of the computer cooling system. All those requirements pose serious challenges for the VR design.
To meet the transient requirements, the concept of adaptive voltage position (AVP) design was invented. Prior to this idea emerged, feedback control regulates the output voltage at a single point for the entire load range. As a result, the output voltage spike during load transient had to be smaller than half of the voltage tolerance window. However, if the output voltage drops with load increasing, the whole voltage tolerance range can be used for the voltage jump or drop during the transient. Another benefit of the AVP design is that the VR output power at full load is reduced, which greatly facilitates the thermal design. If the transients between the two steady states have no spikes and no oscillations, the AVP design is optimal. The relation between the current and output voltage waveform reveals that the VR can be modeled as an ideal voltage source in series with a resistor Ro. In frequency domain, the output impedance of VR should keep constant from DC to high frequency.
In recent years the output current has increased while output voltage decreased. More and more space of the motherboard will be occupied by VRs, especially the output capacitors. It seems that high frequency is becoming the only solution to increase power density and save space. However, the conventional interleaving buck converter's performance suffers a lot as switching frequency increases. The main reason is that switching loss increases proportionally to frequency. Eventually the heat caused by power loss will reach the system designed thermal limit.
Transient voltage clamp (TVC) works in parallel with the switching regulator to achieve fast voltage regulation without bulk capacitors. At the mean time, switching frequency of main VR needs not to be increased. Traditional switch-mode regulators suffer from its slow transient response due to limited control bandwidth hence large output voltage spike. TVC is a parallel branch that will replace the bulk capacitors. Therefore, its AC output impedance should also match the impedance of bulk capacitors. According to the relationship between the parallel impedances on the microprocessor power delivery path, dynamic branch currents distribution causes high TVC current during load transient. A non-linear TVC control scheme is then proposed to achieve highest VR inductor current slew rate during load transient. The power loss in the TVC circuits is the key issue which will prevents TVC from industrial applications. An extended total efficiency is defined as output energy divided by input energy during a period of time. By replacing the bulk capacitors with linear-type TVC, an extra loss is added. It seems that this TVC loss is directly proportional to load transient frequency. Under such assumption, total efficiency degrades as load transient frequency increases. However further analysis with related to parallel impedances shows that this is not true. Due to high impedance at higher frequency, TVC will not respond to such high load transients. The maximum power loss in TVC is limited by the second "zero" of its impedance.
A two channel VR was built to evaluate the TVC performance in terms of transient response and power loss. Experimental results verified the aforementioned concepts and non-linear control scheme. Measured power loss in TVC is low and the transient response is comparable with the traditional bulk capacitors solution.|
|Appears in Collections:||Theses|
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