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Title: Design of DDR2 Interface for Tezzaron TSC8200A Octopus Memory intended for Chip Stacking Applications
Authors: Bapat, Ojas Ashok
Advisors: Dr. W. Rhett Davis, Committee Member
Dr. Eric Rotenberg, Committee Member
Dr. Paul D. Franzon, Committee Chair
Keywords: Memory Controller
DDR2 Controller
3D memory
Issue Date: 14-May-2010
Degree: MS
Discipline: Computer Engineering
Abstract: This document talks about the design of a DDR2 Controller for the Tezzaron TSC8200A (Octopus) High-Speed Self-Repairing L3 Memory which is intended for chip stacking applications. The controller is the part of a LEON3 processor architecture. The system consists of three leon processor cores connected to all the peripherals and memory through an AMBA-2.0AHB/APB Master/Slave bus interface. The development environment is the gaisler open source library which is a set of reusable IP cores designed for system on chip development. The advantage of using this environment is that the libraries are technology independent and can be used with various target technologies and CAD tools. The DDR2 controller acts as a slave to the AHB bus. On the other side is the Tezzaron Octopus Memory. The controller consists mainly of two parts; one which implements the state machines for both the AHB side interface and the Memory side interface and the other which does the job of shifting, alignment and conversion of signals from single to double data rate. This part also has the pads instantiated in it. As the Octopus Memory has two independent ports which are seen as two separate parallel memories by the host processor, we have two instantiations of the controller in the design. Also, unlike conventional DDR2 standards, the Octopus Memory uses only single ended signals. Also, since this memory has been specially designed for stacking, it does not support/require on-die termination and off-chip driver capability. Here, we talk about the challenges faced in the design of the Controller state machines, the physical interface, synthesis and the functional and timing verification of the DDR2 controller. Also, we talk about the place and route strategy adopted to layout the entire 3-core processor architecture along with the controller and memory. Since the Tezzaron Octopus memory IP was not available at the time, we have used a dummy .lef block for it. Assertion based formal verification techniques were used the verify the outputs and internal signals of the controller. The design was synthesized in IBM 130nm technology library with artisan memories and I/O pads. The total synthesized area of the entire user logic is 7.01 mm2 without the macros and pads. The standard cell area for just the controller is 4.89 mm2 . The total die size for the user logic with the macros and pads is 7mm x 7mm with a core utilization of 0.7. Having memory on a separate die helps us get all the benefits of an on chip memory while reducing the complexity and number of process steps. The memory and the user logic can be can be individually processed in different feature sizes or even different materials. The dies can be than stacked on top of each other and connected with through silicon vias. The Octopus memory follows the IMIS interface specification which defines a high bandwidth 1024-bit wide vertical bus at the memory surface. This allows for shorter interconnects, thus greatly reducing the latency. It improves the bandwidth by allowing up to eight parallel 64 bit double pumped data ports.
URI: http://www.lib.ncsu.edu/resolver/1840.16/6346
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