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Please use this identifier to cite or link to this item: http://www.lib.ncsu.edu/resolver/1840.16/984

Title: Design and implementation of a Digital Controller for High Power Converters
Authors: Mundkur, Sameer Shailesh
Advisors: Dr. Alex Q. Huang, Committee Chair
Dr. Mesut Baran, Committee Member
Dr. Subhashish Bhattacharya, Committee Member
Keywords: FPGA
Verilog
DSP
Power Electronics Controller
Issue Date: 11-Nov-2008
Degree: MS
Discipline: Electrical Engineering
Abstract: Multi-level converter topologies are widely used in utility power electronics as it offers improved reliability, multiple layers of protection, flexibility of expansion and isolation. This thesis proposes to design and implement a distributed control topology for high power electronics which consists of centralized controller which would process various power electronic related signals like voltage, current, switching device temperatures as well as several localized controllers which communicate with the central controller and generate gate drive signals for each high power switching device/ bridge converter. So there is essentially a two layer hierarchy – the complex digital signal processing and modulation algorithms are done at the central controller level and the switching modulation signals are then sent to several localized controllers which then process this data and control the power electronics. The central controller provides the supervisory control while the actual device level control is delegated to several local controllers. This topology provides flexibility as well as a robust communication scheme between controllers. This thesis also looks at a shared control algorithm computation approach by moving some of the computation from the DSP to the FPGA for faster processing and generation of gate drive control. This implementation of an intelligent modular controller would result in better performance and fault-response time through the exploitation of parallelism inherent in a programmable hardware based controller approach. The design will be captured using verilog HDL and synthesized on a FPGA.
URI: http://www.lib.ncsu.edu/resolver/1840.16/984
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