Browsing by Author "Alexander G. Dean, Committee Member"

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    Analysis-Managed Processor (AMP): Exceeding the Complexity Limit in Safe-Real-Time Systems
    (2006-04-28) Anantaraman, Aravindh Venkataseshadri; Alexander G. Dean, Committee Member; Frank Mueller, Committee Member; Thomas M. Conte, Committee Member; Eric Rotenberg, Committee Chair
    Safe-real-time systems need tasks' worst-case execution times (WCETs) to guarantee deadlines. With increasing microarchitectural complexity, the analysis required to derive WCETs is becoming complicated and, in some cases, intractable. Thus, complex microarchitectural features are discouraged in safe-real-time systems. My thesis is that microarchitectural complexity is viable in safe-real-time systems, if control is provided over this complexity. I propose a reconfigurable processor, the Analysis-Managed Processor (AMP), that offers complete control over its complex features. The ability to dynamically manage the AMP enables novel cooperative static and run-time WCET frameworks that break the limitations of the traditional static-only WCET model, allowing complex features to be safely included. (i) The Virtual Simple Architecture (VISA) framework avoids analyzing complex features. VISA derives tasks' WCETs assuming a simple processor. At run-time, tasks are speculatively attempted on the AMP with complex features enabled. A run-time framework dynamically confirms that WCETs are not exceeded. (ii) The Non-Uniform Program Analysis (NUPA) framework enables efficient analysis of complex features. NUPA matches different program segments to different operating modes of the AMP. NUPA yields reduced WCETs for program segments that can be analyzed in the context of complex features, without the severe burden of requiring all program segments to be analyzed this way. I propose that out-of-order execution is not inherently intractable, rather its interaction with control-flow is intractable. Out-of-order processors overlap the execution of 10s to 100s of in-flight instructions. Variable control-flow causes an explosion in the number of potential overlap schedules. I propose two timing analysis techniques that reduce the number of possible schedules. (i) Repeatable Execution Constraints for Out-of-ORDER (RECORDER) eliminates variable control-flow and implied data-flow variations, guaranteeing a single input-independent execution schedule that can be derived via simulation, using arbitrary (random) program inputs. (ii) Drain-and-Branch (DNB) restricts instruction overlap by insulating a branch's control-dependent region from the effects of instructions before and after the region. RECORDER and DNB are complementary, as they work well for branches with short regions and long regions, respectively. Further, in the context of a NUPA framework, different branch regions may favor RECORDER, DNB, or in-order execution mode of the AMP, for achieving a highly optimized overall WCET. Moreover, branch regions analyzed for downgraded in-order execution can still benefit from the VISA run-time framework by speculatively enabling out-of-order mode of the AMP. The flexible combination of all the above techniques multiplies benefits, yielding a powerful framework for fully and safely capitalizing on complex microarchitectures in safe-real-time systems.
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    Energy Optimization in Sensor Networks
    (2007-11-06) Chiang, Mu-Huan; Peng Ning, Committee Member; Gregory T. Byrd, Committee Chair; Mihail Sichitiu, Committee Member; Alexander G. Dean, Committee Member
    Recent advances in wireless communications and computing technology are enabling the emergence of low-cost devices that incorporate sensing, processing, and communication functionalities. A large number of these devices are deployed to create a sensor network for both monitoring and control purposes. Sensor networks are currently an active research area mainly due to the potential of their applications. However, the operation of large scale sensor networks still requires solutions to numerous technical challenges that stem primarily from the constraints imposed by simple sensor devices. Among these challenges, the power constraint is the most critical one, since it involves not only reducing the energy consumption of a single sensor but also maximizing the lifetime of an entire network. The network lifetime can be maximized only by incorporating energy awareness into every stage of sensor network design and operation, thus empowering the system with the ability to make dynamic tradeoffs among energy consumption, system performance, and operational fidelity. Optimizing the energy usage is a critical challenge for wireless sensor networks (WSNs). The requirements of energy optimization schemes are as follows. (1) Low individual energy consumption: Sensor nodes can use up their limited energy supply, carrying out computations and transmission. In typical WSNs, nodes play a dual role as both data sender and data router. Malfunctioning of some sensor nodes due to power failure can cause significant topological changes and may require rerouting of packets and network reorganization. Therefore, reducing the energy consumption of each sensor node is critical for WSNs. (2) Balanced energy usage: While minimizing the energy consumption of individual sensor nodes is important, the energy status of the entire network should also be of the same order. If certain nodes have much higher workload than others, these nodes will drain off their energy rapidly and adversely impact the overall system lifetime. The workload of sensors should be balanced in order to achieve longer system lifetime. (3) Low computation and communication overhead: The resource limitations imposed by sensor hardware call for simple protocols that require minimal processing and a small memory footprint. The extra computation and communication introduced by the energy optimization schemes must also be kept low. Otherwise, energy required to perform the optimization schemes may outweigh the benefits. This thesis concentrates on the energy optimization issues in wireless sensor networks. We study the power consumption characteristics of typical sensor platforms, and propose energy optimization schemes in network and application level. We design distributed algorithms that reduce the amount of data traffic and unnecessary overhearing waste in WSNs, and further propose load balancing mechanisms that alleviate the unbalanced energy usage and prolong the effective system lifetime. At the network level, Adaptive Aggregation Tree (AAT) is proposed to dynamically transform the routing tree, using easily-obtained overheard information, to improve the aggregation efficiency. The local adaptivity of AAT achieves significant energy reduction, compared to the shortest-path tree where aggregation occurs opportunistically. We also propose Neighborhood-Aware Density Control (NADC), which exploits the overheard information to reduce the unnecessary overhearing waste along routing paths. In NADC, nodes observe their neighborhood and adapt their participation in the multihop routing topology. By reducing the node density near the routing paths, the overhearing waste can be reduced, and the extremely unbalanced energy usage among sensor nodes is also alleviated, which results in a longer system lifetime. The unbalanced energy usage problem is further addressed at the application level, where we propose Zone-Repartitioning (Z-R) for load balancing in data-centric storage systems. Z-R reduces the workload of certain hot-spots by distributing their communication load to other nodes when the event frequency of certain areas is much higher than the others.
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    Hard-Real-Time Multithreading: A Combined Microarchitectural and Scheduling Approach.
    (2006-05-04) El-Haj Mahmoud, Ali Ahmad; Alexander G. Dean, Committee Member; Eric Rotenberg, Committee Chair; Thomas M. Conte, Committee Member; Frank Mueller, Committee Member
    Simultaneous Multithreading (SMT) enables fine-grain resource sharing of a single superscalar processor among multiple tasks, improving cost-performance. However, SMT cannot be safely exploited in hard-real-time systems. These systems require analytical frameworks for making worst-case performance guarantees. SMT violates simplifying assumptions for deriving worst-case execution times (WCET) of tasks. Classic real-time theory uses single-task WCET analysis, where a task is assumed to have access to dedicated processor resources, hence, its WCET can be derived independent of its task-set context. This is not true for SMT, where tasks interfere due to resource sharing. Modeling interference requires whole task-set WCET analysis, but this approach is futile since co-scheduled tasks vary and compete for resources arbitrarily. Thus, formally proving real-time guarantees for SMT is intractable. This dissertation proposes flexible interference-free multithreading. Interference-free partitioning guarantees that the performance of a single task is not affected by its workload context (hence, preserving single-task WCET analysis), while flexible resource sharing emulates fine-grain resource sharing of SMT to achieve similar cost-performance efficiency. The Real-time Virtual Multiprocessor (RVMP) paradigm virtualizes a single superscalar processor into multiple interference-free different-sized virtual processors. This provides a flexible spatial dimension. In the time dimension, the number and sizes of virtual processors can be rapidly reconfigured. A simple real-time scheduling approach concentrates scheduling within a small time interval (the 'round'), producing a simple repeating space/time schedule that orchestrates virtualization. Worst-case schedulability experiments show that more task-sets are provably schedulable on RVMP than on conventional rigid multiprocessors with equal aggregate resources, and the advantage only intensifies with more demanding task-sets. Run-time experiments show RVMP's statically-controlled coarser-grain resource sharing is as effective as unsafe SMT, and provides a real-time formalism that SMT does not currently provide. RVMP's round-based scheduling enables other optimizations for safely improving performance even more. A framework is developed on top of RVMP to safely, tractably, and tightly bound overlap between computation and memory accesses of different tasks to improve worst-case performance. This framework captures the throughput gain of dynamic switch-on-event multithreading, but in a way that is compatible with hard-real-time formalism.