Browsing by Author "Angus Kingon, Committee Chair"

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Epitaxial Oxide Growth on Si(001) for Floating Epitaxy, a Novel Process for Silicon-on-Insulator Wafer Production
(2007-03-08) Hydrick, Jennifer Marie; Angus Kingon, Committee Chair; Veena Misra, Committee Member; Mark Johnson, Committee Member
As scaling continues in the semiconductor industry, silicon-on-insulator (SOI) wafers are increasingly becoming the substrate of choice, due to higher channel mobility, effective device isolation, reduced short channel effects, minimized parasitic capacitance, and therefore higher speed, compared to a regular silicon wafer. Current methods of SOI wafer production, however, will have difficulty achieving the desired silicon device layer and buried oxide insulator layer thicknesses and eliminating interface roughness as scaling proceeds. We propose "Floating Epitaxy SOI" as a novel method of SOI production utilizing an all in-situ growth process. Floating Epitaxy SOI involves Molecular Beam Epitaxy deposition of an epitaxial template oxide, oxidizing through the epitaxial template layer to establish the insulation layer, and silicon growth on top of the epitaxial template oxide layer (which is now "floating" on top of an amorphous oxide layer). The key to this process is the epitaxial oxide template layer, which must deposit on the silicon substrate as an atomically smooth film with a lattice parameter close to that of silicon and must be sufficiently stable in both an oxygen an in vacuum annealing to relatively high temperature to achieve Floating Epitaxy SOI. Although many researchers have examined epitaxial oxides on silicon, this study focuses on epitaxial films over large area substrates, while virtually all other studies report on growth on small substrate sizes. Also, the oxide stability limits on silicon in vacuum have not been thoroughly established by previous work, and are investigated here. The growth and thermal stability of this epitaxial oxide template layer are discussed, as well as brief results for through-oxidation "floating" of the template oxide layer and silicon growth experiments. BaO, SrO, CaO, Ba[subscript 1-x]Sr[subscript x]O, SrTiO₃, CaTiO₃, and Ca[subscript 1-x]Sr[subscript x]TiO₃ were successfully epitaxially deposited on Si(001) substrates. A 64:36 Ba:Sr ratio was used for the solid solution of Ba[subscript 1-x]Sr[subscript x]O, in order to achieve close lattice matching with silicon; a 50:50 Ca:Sr ratio was used initially for the Ca[subscript 1-x]Sr[subscript x]TiO₃ solid solution, an attempt to mediate SrTiO₃'s 2% lattice mismatch with silicon and CaTiO₃'s orthorhombic structure. Alloying SrTiO₃ with calcium to alter the lattice parameter has not been studied much to this point in thin films, and this is the first demonstration of Ca[subscript 1-x]Sr[subscript x]TiO₃ and CaTiO₃ thin films grown directly on silicon. Reflection High Energy Electron Diffraction patterns of both Ba[subscript 1-x]Sr[subscript x]O and Ca[subscript 1-x]Sr[subscript x]TiO₃ indicated high quality 2D epitaxial films. A thin (3 monolayer) film of Ba[subscript 1-x]Sr[subscript x]O is stable on silicon to 535°C in vacuum, while a 5 monolayer Ca[subscript 1-x]Sr[subscript x]TiO₃ film survives to 740°C in vacuum, but roughens from a 2D toward a 3D surface above ˜650°C. Of the epitaxial oxides studied, the solid solution Ca[subscript 1-x}Sr[subscript x]TiO₃ would be the best choice for Floating Epitaxy SOI, based on epitaxial growth quality and stability. High-resolution TEM indicates the presence of an amorphous interfacial layer at the SrTiO₃Si interface, as grown. X-ray diffraction confirms an epitaxial film, with a lattice parameter larger than that of bulk SrTiO₃, likely due to oxygen deficiency in the film. Annealing 17.5nm SrTiO₃Si(001) at 800°C in 5.5 Torr of oxygen for 30 minutes results in an equivalent oxide thickness of 10.3nm, sufficient for scaling to 2020. X-ray diffraction after annealing reveals a still-epitaxial SrTiO₃ film, with sharper 2θ and χ peaks and a lattice parameter closer to that of bulk SrTiO₃. These results validate the "floating" epitaxy approach: an epitaxial film remains on top of an amorphous insulator, after through-oxidation of the substrate. Direct deposition of epitaxial silicon on Ca[subscript 1-x]Sr[subscript x]TiO₃ and solid-phase epitaxy of silicon on a CaTiO₃ film are promising, but interface engineering or a surfactant may be required to achieve a high quality, single crystal silicon layer.
Lanthanide-based Oxides and Silicates for High-K Gate Dielectric Applications
(2007-07-27) Jur, Jesse Stephen; Angus Kingon, Committee Chair; Gregory Parsons, Committee Member; Jon-Paul Maria, Committee Member; Mark Johnson, Committee Member
The ability to improve performance of the high-end metal oxide semiconductor field effect transistor (MOSFET) is highly reliant on the dimensional scaling of such a device. In scaling, a decrease in dielectric thickness results in high leakage current between the electrode and the substrate by way of direct tunneling through the gate dielectric. Observation of a high leakage current when the standard gate dielectric, SiO2, is decreased below a thickness of 1.5 nm requires engineering of a replacement dielectric that is much more scalable. This high- dielectric allows for a physically thicker oxide, reducing leakage current. Integration of select lanthanide-based oxides and silicates, in particular lanthanum oxide and silicate, into MOS gate stack devices is examined. The quality of the high-K dielectrics is monitored electrically to determine properties such as equivalent oxide thickness, leakage current density and defect densities. In addition, analytical characterization of the dielectric and the gate stack is provided to examine the materialistic significance to the change of the electrical properties of the devices. It is shown that optimization of low-temperature processing can result in MOS devices with an equivalent oxide thickness (EOT) as low 5 Å and a leakage current density of 5.0 A⁄cm2. High-temperature processing, consistent with a MOSFET source-drain activation anneal, yields MOS devices with an EOT as low as 1.1 nm after optimization of the TaN/W electrode properties. The decrease in the device effective work function (phi_M,eff) observed in these samples is examined in detail. First, as a La2O3 capping layer on HfSiO(N), the shift yields ideal-phi_M,eff values for nMOSFET deices (4.0 eV) that were previously inaccessible. Other lanthanide oxides (Dy, Ho and Yb) used as capping layers show similar effects. It is also shown that tuning of phi_M,eff can be realized by controlling the extent of lanthanide-silicate formation. This research, conducted in conjunction with SEMATECH and the SRC, represents a significant technological advancement in realizing 45 and sub-45 nm MOSFET device nodes.
Lead Zirconate Titanate (PZT) Based Thin Film Capacitors For Embedded Passive Applications
(2003-08-21) Kim, Taeyun; Robert Croswell, Committee Member; Paul Franzon, Committee Member; Jon-Paul Maria, Committee Chair; Gerd Duscher, Committee Member; Angus Kingon, Committee Chair
Investigations on the key processing parameters and properties relationship for lead zirconate titanate (PZT, 52/48) based thin film capacitors for embedded passive capacitor application were performed using electroless Ni coated Cu foils as substrates. Undoped and Ca-doped PZT (52/48) thin film capacitors were prepared on electroless Ni coated Cu foil by chemical solution deposition. The effects of processing parameters on the phase evolution, microstructures, dielectric properties, and reliability were investigated. Electroless Ni coated Cu foil was selected as substrate for its low cost, oxidation resistance and lamination capability. When annealed at 450 °C, electroless Ni coated Cu foil showed transformation from amorphous Ni to crystalline phase of Ni-P (mostly Ni₃P) and Ni metal. For PZT (52/48) thin film capacitors on electroless Ni coated Cu foil, voltage independent (zero tunability) capacitance behavior was observed. Dielectric constant reduced to more than half of the identical capacitor processed on Pt/SiO₂/Si. Dielectric properties of the capacitors were mostly dependent on the crystallization temperature. Capacitance densities of almost 350 nF/cm² and 0.02-0.03 of loss tangent were routinely measured for capacitors crystallized at 575-600 °C. Leakage current showed dependence on film thickness and crystallization temperature. It is speculated that space charge limited conduction (SCLC) seems to be consistent with conduction mechanism in PZT thin films on electroless Ni. From a two-capacitor model, the existence of a low permittivity interface layer (permittivity -30) was suggested. Also it is suggested a high concentration of traps exist inside the PZT capacitor. Interface reaction between PZT thin film and electroless Ni was suggested to be responsible for measured electrical properties. The interfacial layer might be composed of unreacted oxide, phosphate, and phosphides possibly from phosphorous diffused from electroless Ni into PZT bulk. For Ca-doped PZT (52/48) thin film capacitors prepared on Pt, typical ferroelectric and dielectric properties were measured up to 5 mol%Ca doping. Further addition up to 10 mol % changed the lattice parameter of the unit cell, and reduced dielectric properties were observed. The possibility of Ca acceptor doping is suggested. When Ca-doped PZT (52/48) thin film capacitors were prepared on electroless Ni coated Cu foil, phase stability was influenced by Ca doping and phosphorous content. Dielectric properties showed dependence on the crystallization temperature and phosphorous content. Capacitance density of -400 nF/cm² was achieved, which is an improvement by more than 30% compared to undoped composition. Ca doping also reduced the temperature coefficient of capacitance (TCC) less than 10%, all of them were consistent in satisfying the requirements of embedded passive capacitor. Leakage current density was not affected significantly by doping. Interface control by controlled pO² crystallization was found to be not effective in interface layer mitigation. Phase purity, dielectric properties, surface microstructure, and pO² were found to have a correlated dependence. To tailor the dielectric and reliability properties, ZrO² was selected as buffer layer between PZT and electroless Ni. Only RF magnetron sputtering process could yield stable ZrO² layers on electroless Ni coated Cu foil. Other processes resulted in secondary phase formation, which supports the reaction between PZT capacitor and electroless Ni might be dominated by phosphorous component. Incorporation of ZrO² layers reduced maximum capacitance density by 10 %(- 350 nF/cm²) due to lower permittivity of ZrO² layer. Significantly improved leakage current densities were measured for PZT thin film capacitors on ZrO₂. For PZT thin film capacitors incorporating 100 nm thick ZrO₂ layer, leakage current density of 10⁻⁸ A/cm² was measured at 25 VDC, which is more than three orders of magnitude lower than those directly deposited on electroless Ni coated Cu foil. The complete set of experimental data provides validation and process conditions for the use of PZT thin films on low cost electroless Ni coated Cu foil substrate as embedded capacitors in high density printed circuit boards.
Piezoelectric, Dielectric and Ferroelectric Thin Films on Metal Substrates for Microelectronic Applications
(2006-10-06) Srinivasan, Sudarsan; Angus Kingon, Committee Chair
The purpose of this research has been to demonstrate the possibility of integrating piezoelectric, dielectric and ferroelectric- lead and barium based oxide thin films and PVDF polymer on flexible metal substrates for microelectronic applications. Investigations on the key processing parameters and properties relationship for lead zirconate titanate (PZT, 52⁄48) and barium zirconate titanate (BZT, 35⁄65) based thin films on Cu foils were performed and studied. The impact of the oxygen partial pressure on the electrical properties of PZT and BZT thin films during processing has been explored, and demonstrated that high quality films and interfaces can be achieved through control of the pO2 within a window predicted by thermodynamic stability considerations. It should be noted that the high temperature processing of barium based ferroelectric oxides can be processed on Cu foils in a wider window of pO2 compared to that of processing lead based ferroelectric oxides. Also, the high volatile nature of lead makes the processing of lead based ferroelectric oxides difficult. Considering these issues, this work shows the processing technique undertaken to achieve high quality barium and lead based oxide thin films on Cu foils. The demonstration has broad implications, opening up the possibility of the use of low cost, high conductivity copper electrodes for a range of Pb-based and Ba-based perovskite materials, including PZT films in embedded printed circuit board applications for capacitors, varactors, and sensors; multilayer PZT piezoelectric stacks; and multilayer lead magnesium niobate-lead titanate-based dielectric and electrostrictive devices. In the case of ferroelectric PZT films on Cu foil, the capacitors do not fatigue upon repeated switching like those with Pt noble metal electrodes. Instead they appear to be fatigue-resistant like ferroelectric capacitors with oxide electrodes. This may have implications for ferroelectric nonvolatile memories. The effect of electrodes on the electrical properties of lead zirconate titanate has been investigated and discussed. For systematic and comprehensive analysis of the electromechanical properties, an accurate analytical modeling has been developed. The analytical modeling derived can be applied to double end clamped (under various end conditions) beam geometry that is useful for the case of compliant actuator material (eg. PVDF polymers) and applications, that involve high resonance of operation. These analytical expressions represent the first set of derivations for flexural mode actuators under dynamic conditions, which yield both the resonant frequencies and the displacement at resonance of double end clamped piezoelectric actuators. These analytical expressions allow users to optimize the materials selection and dimensions of bimorph and unimorph actuators. The reliability of the analytical expressions derived has been investigated using experimental results performed on PVDF polymer as a piezoelectric actuator. The actuators were constructed as double end clamped beams (both bimorph and unimorph cases). They were operated in flexural mode. The two ends of the actuator were clamped such that the slope at both the ends of the actuator bending curvature at resonance is zero. This type of end condition results in increasing the resonance frequency.
Thin Film Shape Sensing: The Development of an Integrated Flexible Thin Film Temperature-Compensated Strain Sensing Array
(2006-09-25) Hydrick, Aaron Eugene; Herbert Eckerlin, Committee Member; Ronald Scattergood, Committee Member; Angus Kingon, Committee Chair
The purpose of the Thin Film Shape Sensing project was to develop an array of temperature-compensated strain sensors to be used as a shape sensing array capable of detecting changes in the shape of surfaces such as airfoils. In the case of morphing surface technology, this type of sensor array would provide the necessary feedback to remotely sense and control the shape of the surface. This project has employed the use of NiChrome (80% Ni, 20% Cr) strain gages and NiChrome/Platinum paired element thermistors for temperature sensing. The sensors were initially developed on DuPont Kapton® and later on a different DuPont polyimide substrate provided by Cirexx®. Three prototype arrays have been developed and tested for basic functionality. The first prototype was designed, built and tested. Basic sensor functionality (electrical response to strain and temperature) was shown. After a substantial redesign including sensor size reduction and processing refinements intended to improve the sensor properties, a second array was produced and tested, showing improved sensor performance and overall array functionality. A third and final prototype was fabricated at 1⁄2 the original linear dimensions of the second array to show scalability of the array's features. Overall, this prototype was also functional with sensor properties similar to the full-size prototype.