Browsing by Author "DR. Vincent W. Freeh, Committee Member"

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    Development of a Cycle Level, Full System, x86 Microprocessor Simulator
    (2008-03-24) Gambhir, Mohit; Dr. Yan Solihin, Committee Chair; Dr. Eric Rotenberg, Committee Member; DR. Vincent W. Freeh, Committee Member
    Although x86 processors are the most popular processors in commercial and scientific working environment, there is a scarcity of open source microprocessor simulators that can enable researchers to experiment with new x86 based microprocessor and memory system designs. Also, most of the simulators that exist today are user space simulators that do not profile the operating system code that gets executed when interrupts and system calls are invoked while an application is running. This work involves the development of a cycle level, full system, x86 microprocessor simulator called MYSim. One of the biggest challenges involved in developing an x86 based processor simulator is that the x86 instruction set is complex. Its complexities include variable length instructions that may take varying number of cycles to decode. Also, the operands in an x86 instruction may reside in registers or in memory or both. These complexities make the x86 instruction set architecture (ISA) particularly hard to simulate. MYSim is an execution driven simulator that divides the simulation in two parts: the first part is the functional simulator or emulator, which actually executes the simulated application as well as the OS code and the second part is the timing simulator, which models the timing of the application. MYSim uses Bochs (an open source x86 emulator) as the functional simulator which emulates x86 processors, hardware devices, memory, etc. and enables the execution of various operating systems and software within the emulation. MYSim's timing simulator is ported from SESC (SuperESCalar Simulator), a simulator that initially supported MIPS ISA and was modified, as part of this work, to support x86 ISA. The functional simulator executes the next x86 instruction, breaks it into μops and feeds those μµops to the timing simulator. The timing simulator models a full out of order pipeline with branch prediction, caches, buses and most major components that are required to be simulated in order to model accurate timing of modern microprocessors.