Browsing by Author "Dennis Bahler, Committee Member"

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Evidence-Based Trust in Distributed Agent Systems
(2009-01-21) Wang, Yonghong; Greg Byrd, Committee Member; Ting Yu, Committee Member; Dennis Bahler, Committee Member; Munindar Singh, Committee Chair
Trust is a crucial basis for interactions among parties in large, open distributed systems. Yet, the scale and dynamism of such systems make it infeasible for each party to have a direct basis for trusting another party. For this reason, the participants in an open system must share information about trust. Traditional models of trust employ simple heuristics and ad hoc formulas, without adequate mathematical justification. These models fail to properly address the challenges of combining trust from conflicting sources, dealing with malicious agents, and updating trust. This dissertation understands an agent Alice's trust in an agent Bob in terms of Alice's certainty in her belief that Bob is trustworthy. Unlike previous approaches, this dissertation formulates certainty in terms of a statistical measure defined over a probability distribution of the probability of positive outcomes. Specifically this dissertation makes the following contributions. It 1. Develops a mathematically well-formulated approach for an evidence-based account of trust; proves desirable properties of certainty; and establishes a bijection between evidence and trust. 2. Defines a concatenation, an aggregation, and a selection operator to propagate trust, and proves desirable properties of these operators. 3. Develops trust update mechanisms and formally analyzes their properties. 4. Extends the definition of certainty from binary events to multivalued events. Establishes a bijection between Dempster-Shafer belief space and evidence space, and defines a novel combination operator, which is commutative and associative. In contrast with traditional combination operators, which ignore conflict and sometimes yield counterintuitive results, the proposed operator treats conflict naturally.
Exploring Bimanual Tool-Based Interaction in a Drawing Environment
(2004-05-28) Butler, Colin Grant; Robert A. St. Amant, Committee Chair; Dennis Bahler, Committee Member; R. Michael Young, Committee Member
In this document, I will present HabilisDraw DT, a drawing environment in which bimanual direct manipulation and a strong tool-use metaphor are supported via the DiamondTouch input device from Mitsubishi Electronics Research Lab. The goal of this research is to explore the viability of the various contributions of HabilisDraw DT in the development of future interfaces. The principles upon which HabilisDraw DT have been built include persistent tools that embody intuitive aspects of their physical counterparts and an approach to interface learnability that capitalizes on the user's inherent ability to use tools both separately and in conjunction with other tools. In addition to these principles, HabilisDraw DT extends the physical-virtual tool correlation with bimanual input via the MERL DiamondTouch input device and a close adherence to the direct manipulation interaction model. This paper presents background work in novel interaction and an overview of the HabilisDraw interface, then explores the benefits of a desktop metaphor that closely mimics the behavior of tools and objects in a two-dimensional drawing environment and argues for the applicability of the system's fundamental principles for improving interface usability in the future.
Flip Chip testing with a capacitive coupled probe chip.
(2003-03-12) Stanaski, Andrew; Dennis Bahler, Committee Member; Rhett Davis, Committee Member; Wentai Liu, Committee Member; Paul Franzon, Committee Chair
Testing integrated circuits that employ an area array of I/O presents unique challenges because the face of the chip is not visible for probing. On chips that use perimeter bond pads the face of the chip is exposed, so signals on the wiring in the top layer metal may be probed while the chip is in operation. This is not possible when the face of the chip is hidden. This work proposes a way to probe test points on the top layer metal of chips that use area I/O. The method works by attaching the chip to a specially designed probe chip instead of the normal packaging. Metal pads on the top layer of the probe chip correspond to lines on the top layer of the chip being tested. These points form a capacitive coupling between the chips, letting the probe chip read the signals at the test points. This leaves the original chip largely unchanged, and allows critical signals to be probed. The geometry of the test points is examined and evaluated using a field solver for their potential to couple between the chips. A square section of metal roughly 6 mm on a side provides 1 fF coupling capacitance, enough for a receiver on the probe to reproduce the signal. The work continues with the design of a receiver circuit to amplify the small input from the test points. The receiver employs a differential amplifier followed by an inverter to amplify the signal without excessive loading at the input. Simulations of the receiver demonstrate its ability to recreate the signal. Additional simulations measure the performance of the receiver under varying conditions, and explore the operational characteristics. This work also describes the design of a four issue superscalar microprocessor that was used as a reference for explorations of systems design for multichip modules (MCMs). This work focused on the chip testing aspect of area array I/O chips used in an MCM. Other work investigated partitioning, routing, and other system design issues. Finally, the work gives an outline of the CAD tool setup created for use at N. C. State University. The design kit created supports research as a vehicle for creating chips, and for integrating research CAD algorithms.
Investigating Complexity Metrics as Indicators of Software Vulnerability.
(2010-12-09) Shin, Yonghee; Laurie Williams, Committee Chair; Mladen Vouk, Committee Member; Dennis Bahler, Committee Member; Jason Osborne, Committee Member
Minimum Linear Arrangement of Trees
(2002-09-12) Hochberg, Robert; Matthias F. M. Stallmann, Committee Chair; Dennis Bahler, Committee Member; Carla Savage, Committee Member
In the minimum linear arrangement problem one is given a graph, and wishes to assign distinct integers to the vertices of the graph so that the sum of the differences (in absolute value) across the edges of the graph is minimized. This problem is known to be NP-complete for the class of all graphs, but polynomial for special classes of graphs, one of which is the class of trees. For trees on n vertices, algorithms of time complexity O(n2.2) and O(n1.6) were given by Shiloach in 1979 and Chung in 1983 respectively, with no improvement since then. In this thesis, we present a linear-time algorithm for finding the optimal embedding among those embeddings which have no "crossings," and we describe a C++ implementation of that algorithm as well as Shiloach's algorithm which we make available to the research community.
Searching for Better Logic Circuits: Using Artificial Intelligence Techniques to Automate Digital Design.
(2006-06-14) Lammert, Adam Crawford; Dennis Bahler, Committee Member; James Lester, Committee Member; Edward Davis, Committee Chair
Logic circuits are at the core of modern computing. The process of designing circuits which are efficient is thus of critical importance. Usually, logic circuits are designed by human beings who have a specific repertoire of conventional design techniques. These techniques limit the solutions that may be considered during the design process in both form and quality. The limits guide designers through the immense realm of possible circuits, thus making the problem more manageable. Simultaneously, the limits sometimes eliminate from consideration circuits which are optimal in terms of size, depth, etc. By exploring the full range of possible solutions, circuits could be discovered which are superior to the best known human designs. Automated design techniques borrowed from artificial intelligence have allowed exactly that. Specifically, the application of genetic algorithms has allowed the creation of circuits which are substantially superior to the best known human designs. This paper expands on such previous research with a three-fold approach. This approach is comprised of (1) two distinct optimizations for the application of genetic algorithms to design, (2) the formulation and implementation of a systematic search technique to the problem and (3) a comparison of the relative merits of the optimized genetic algorithm and the systematic search technique. It is contended that both genetic algorithms and systematic search can be preferable depending on the situation at hand.