Browsing by Author "Dr Paul Franzon, Committee Chair"

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Hardware Efficient Pattern Matching Algorithms and Architectures for Fast Intrusion Detection.
(2006-12-08) Aldwairi, Monther; Dr Paul Franzon, Committee Chair
Intrusion detection processors are becoming a predominant feature in the field of network hardware. As demand on more network speed increases and new network protocols emerge, network intrusion detection systems are increasing in importance and are being integrated in network processors. Currently, most intrusion detection systems are software running on a general purpose processor. Unfortunately, it is becoming increasingly difficult for software based intrusion detection systems to keep up with increasing network speeds (OC192 and 10Gbps at backbone networks). Signature-based intrusion detection systems monitor network traffic for security threats by scanning packet payloads for attack signatures. Intrusion detection systems have to run at wire speed and need to be configurable to protect against emerging attacks. This dissertation describes the concept, structure and algorithms for a special purpose hardware accelerator designed to meet those demands. We consider the problem of string matching which is the most computationally intensive task in intrusion detection. A configurable string matching accelerator is developed with the focus on increasing throughput while maintaining the configurability provided by the software intrusion detection systems. A hardware algorithm for efficient data storage and fast retrieval is used to compress, store and retrieve attack signatures. Our algorithms reduce the size of the rules to fit on chip and enables intrusion detection to run at line rates and faster.
Implementation of ACCI Test Vehicle
(2008-10-29) Lammade, Akalu Lentiro; Dr Paul Franzon, Committee Chair; Dr Rhett Davis, Committee Member; Dr Kevin Gard, Committee Member
The main challenge in commissioning a spacecraft system is the time it takes to design, build, integrate, launch, and bring online a given system. Air Force Research Lab (AFRL) has envisaged transforming these processes into what it calls â€œsix-day spacecraftâ€ in the next decade. The six-day spacecraft is basically getting a spacecraft part up and running in less than a week. This fast method of implementing a spacecraft system based on plug-andâ€“play (PnP) approach, dubbed Space Plug-and-Play Avionics (SPA), will also make the space system more robust in line with an increased requirement for communication channels to have good signal integrity and high-speed data paths, like for a spacecraft radio-frequency (RF) communications with the ground command center and the gunship. AC coupled interconnects (ACCIs) provide transceivers that provide clean and boosted high-speed data by blocking noise (DC components). How good these ACCI channels work can be determined based on Bit Error Rate (BER). We have implemented ACCI Test Vehicle to be used as a high-speed data transceiver inside a spacecraft. An existing Bit Error Rate Test (BERT) system has been upgraded and redesigned to work with the implemented ACCI Test Vehicle to verify data integrity. This thesis mostly focuses on describing the implementation of ACCI Test Vehicle through integration of AppliquÃ© Sensor Interface Module (ASIM) that bridge between Space Plug-and-Play Avionics using USB (SPA-U) and useful services for creating the SPA devices. The redesigned and upgraded FPGA-based application that runs on a PowerPC processor creates stress by sending Pseudo-Random Bit Sequences (PRBS) into several ACCI channels and assesses the performance of these channels. The designed application that had been intended to have a maximum data rate of 3.2Gbps with user-configurable and International Telecommunication Union-Telecommunication section (ITU-T) recommended PRBS test patterns didnâ€™t work and we had to go back to a fallback option that provided relatively lower data rate. The complete system is implemented and tested on the designed ACCI Test Vehicle board running on Virtex II Pro Field Programmable Gate Array (FPGA). The logic modification for the BERT has been made in Verilog as there has been substantial hardware complexity compared to the original BERT design and, due to version upgrades the changes to the C-based drivers were made for the on-chip PowerPC processor to handle hardware routines. The BERT application allows the user to remotely configure the system and see BER test statistics through an RS232 interface. The ACCI Test Vehicle has been designed in two separate multi-layered boards; daughterboard and motherboard. The motherboard houses the ASIM as one of its components for a centralized management of the sensor or the ACCI system for resources, including power management among many other things. This paper tries to show the overall design of the ACCI Test System that provides a full plug-n-play integration with ASIM using Satellite Data Model (SDM). This implemented system demonstrates new simplified dimensions to avionics and digital development challenges.
Speech Recognition Co-processor
(2008-04-02) Chandra, Dhruba; Dr Paul Franzon, Committee Chair; Dr. R. Rodman, Committee Member; Dr E. Rotenberg, Committee Member; Dr. W. Rhett Davis, Committee Member
With computing trend moving towards ubiquitous computing propelled by the advances in embedded mobile processors and battery technology, speech recognition is becoming an essential part of embedded processor I⁄O device. Speech recognition is also used in command and control and automated customer service. Real time speech recognition application is both computation and memory intensive and it overwhelms even a high end multi-gigahertz processor to achieve real time performance. An embedded mobile device cannot support real time large vocabulary speech recognition application as the processors are less aggressive because of tighter power budget. Hardware solution to speech recognition, in the past, have mainly concentrated on buidling specialized hardware or ASIC accelerators to run software speech application faster but have largely ignored design for large vocabulary and power reduction. In this work, we propose a hardware-software co-design for real time large vocabulary speech recognition. Our design has custom ASIC blocks and RAM memories and a low power processor. The processor maintains a high level control over the blocks and processes parts of speech recognition application which is not computation and memory intensive. The custom ASIC computes the Gaussian probability and performs word search in the dictionary. The RAMs are used for storing the intermediate values and states. The design can handle large vocabulary speech recognition in real time on a mobile embedded device. Our word search uses innovative dictionary word layout in memory which reduces bandwidth by a factor of 11 compared to software implementation and by a factor of 4 compared to other ASIC implementation. One unit of our proposed design can perform 4x and 20x better than other proposed design of specialized hardware design for software speech application in computing the Gaussian probability and word search, respectively.
Symbol Recovery Circuit design for deep-space MARS receiver using SOI technology
(2003-12-15) Bharath, Bhaskar; Dr Rhett Davis, Committee Member; Dr Keith Townsend, Committee Member; Dr Paul Franzon, Committee Chair
The motivation for this thesis is to present a design of a symbol recovery circuit for a receiver on a planetary lander vehicle, which would communicate with a low orbit satellite. With the development of advanced propulsion mechanisms and autonomous machines, there has been a great revival of interest in exploration of nearby planets. The Mars rover project aims to land an autonomous vehicle on the surface of Mars, which would be controlled via a datalink with an orbiting satellite. The design of a communication system for this presents a number of issues, including Doppler resistance, Radiation tolerance and minimal power consumption. The design of the receiver uses a new modulation technique known as Double Differential Phase Shift Keying, which provides the inherent robustness to Doppler while consuming low power. A symbol recovery circuit is an essential part of the receiver and extracts clock information from received data which is then used to demodulate data. The symbol recovery circuit for the rover needs to handle multiple bit rates while consuming minimal power. The design of the receiver on a system level and the symbol recovery circuit is described in the thesis. The system was modeled using MATLAB simulink, designed in Verilog/VHDL, synthesized using Synopsys design compiler and converted to SOI using Cadence.