Browsing by Author "Dr. Alexander Dean, Committee Chair"

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Adding Rivalrous Hardware Scheduling to the First Generation FREEDM Systems Communication Platform
(2010-02-22) Sachidananda, Subash Ghattadahalli; Dr. Alexander Dean, Committee Chair; Dr. Frank Mueller, Committee Co-Chair; Dr. Eric Rotenberg, Committee Member
Existing power management systems are hard-wired, slow, unreliable and insecure. By improving the communication framework for power management systems, using Internet and modern communication protocols like IEC61850, Zigbee (IEEE 802.15.4), etc., not only can energy be managed better, but also, the system as a whole can be made faster, secure and reliable. Any communication network has certain important characteristics like delay, range, scalability, network topology, etc., that dictate its effectiveness and usefulness in a particular environment. Delays in various parts of the network is one of the important characteristics that needs to be studied carefully. Network delays can be reduced by not only faster hardware but also better software. Importance also needs to be placed on monitoring power consumption of the devices, and ways to improve power efficiency of the system. In conjunction with that, a first generation communication framework for renewable energy distribution and management system, was set up using a network of embedded boards and personal computers. Various communication protocols and interfaces were tried to prove the versatility and reliability of the entire system. Experiments were conducted to test the range and delays in various parts of the communication network. Having established a platform for the nodes to communicate, investigation was done to implement techniques that could make the nodes more power efficient. One of the ways to stretch the battery life is through addition of an SMPS. However, addition of an SMPS introduces power instability to the system and interferes with normal functioning of sensitive devices like ADC, compass, etc. A processor controlled SMPS was added to the communication platform and its interference with normal functioning of the system was studied. Possible hardware and software approaches to counter this interference are also presented.
Code Motion Techniques for STI in BBCP
(2003-08-31) Vangara, Sunil; Dr. Frank Mueller, Committee Co-Chair; Dr. Mihail Sichitiu, Committee Member; Dr. Alexander Dean, Committee Chair
Software thread integration (STI) helps in hardware to software migration by enabling integration of two independent software threads, which enables execution of the integrated thread in a generic processor. Automation of STI would help in obtaining efficient software versions of many hardware implemented functions. Bit banged communication protocols (BBCP) have been researched for implementation as software threads .Software integration is performed on the different threads of the implementation for obtaining efficient software versions. Though these integrated threads are efficient, these protocols include a message-level thread which is not integrated with any other threads. During integration, cocalls (coroutine calls) are introduced for context switching between integrated threads. The periodic execution requirement of cocalls results in some inefficiency introduced due to idle times introduced in the message level thread between bit level calls. We propose an optimizing algorithm to improve this and distribute the instructions in the message level thread across inter-bit calls to reduce the idle time. Our code optimization algorithm moves code from paths between inter bit calls which are larger (more execution time) to paths between inter bit calls which are smaller (lesser execution time). We adopt data flow analysis techniques similar to those used for partial redundancy elimination and dead code elimination.
Efficiently Adding Secure Communications to Networked Low-End Embedded Systems using Software Thread Integration
(2003-08-31) Ganesan, Prasanth; Dr. Alexander Dean, Committee Chair; Dr. Gregory Byrd, Committee Member; Dr. Mihail Sichitiu, Committee Member
The wide spread acceptance of distributed embedded networks is motivated by factors such as cost, weight and power consumption. Communication protocols or MAC layer protocols can be implemented in software on microcontrollers to save costs in comparison to dedicated chips. Traditional methods for implementing a protocol's lowest layers (sending and receiving bits and bytes) in software incur significant execution time overhead, which limits system efficiency and peak performance, increasing power consumption. An additional constraint on communication is security. Wireless networks in particular require secure channels of communication due to the open nature of the RF medium, which makes them vulnerable to attacks. To provide privacy these networks use security protocols. Cryptographic support is a vital ingredient of these protocols. All data transmitted and received is encrypted or decrypted in real time. This further burdens the system processor, forcing lower network bit-rates or higher processor clock speeds and therefore increasing power consumption. Software Thread Integration (STI) is a software technique which interleaves multiple threads at the machine instruction level. This enables system resources to be used efficiently and eliminates context switch overhead. This technique gives a wonderful opportunity to utilize the free cycles generated in communication protocols by cryptographic algorithms. Real-time work is performed faster, allowing for better throughput rates. Throughput increase is also attained because of more efficient use of the communication channel. Timing constraints of the communication threads are met while cryptographic duties are performed concurrently. This saves many processor cycles as well. In some cases it may also allow hardware to software migration without any effect on the throughput rates. This thesis proposes a set of methods to add cryptographic support efficiently to networked embedded systems using STI and save processor cycles and power. A system level software architecture is proposed to enable the use of integrated threads efficiently. TDMA threads are integrated with encryption/decryption threads and, using the above technique and proposed architecture, implemented as part of an open source operating system AVRX. The results show that an STI based implementation is more efficient in the case of synchronous transmission compared to traditional ISR or busy-wait schemes. Our analysis of an integrated thread including the RC4 stream cipher at a relative bus speed of f[subscript cpu]/16 showed a 22% increase in algorithm throughput while data throughput increased by 23%. Further results and benefits are tabulated and evaluated.
Environment Replay for Low-End Reactive Embedded Systems
(2005-01-06) Seetharam, Adarsh; Dr. Eric Rotenberg, Committee Member; Dr. Frank Mueller, Committee Member; Dr. Alexander Dean, Committee Chair
Existing benchmark suites for embedded systems focus on batch processing applications to simplify portability. However, embedded systems are typically tightly coupled to the external environment through input/output (I/O) operations, resulting in reactive, real-time rather than batch behavior. Furthermore, often the environmental state is not dependent on program progress, so portions of the program may block until an environmental change occurs, limiting the impact of a faster processor or more efficient code. Existing benchmark suites ignore these important aspects, leading to one-dimensional characterizations of embedded systems. This work offers methods to record and play back environmental inputs within the limited resources available on common low-end microcontroller units (MCUs). We modify input operations in the source code at the C level, creating a record version and a replay version. For recording, input data is captured and stored as the program executes. This data is analyzed, compressed and converted off-line into a series of time-dependent events. During replay, the input operations read the compressed environmental input event data, rather than the environment. These changes allow virtualization of input operations, resulting in C code which can easily be ported to different processors for batch-mode performance evaluation, yet still react to the original event timeline. Our methods are demonstrated with a universal infrared remote control application. Environmental inputs are recorded on an 8-bit MCU, processed and replayed. We then evaluate the impact of a higher clock rate and also porting to a 16-bit MCU. We characterize memory requirements, response times and the implications of porting interrupts.
Stack Space Analysis for ARM Executables
(2008-05-16) Ramachandran, Shankar; Dr. Xiaosong Ma, Committee Member; Dr. Yan Solihin, Committee Member; Dr. Alexander Dean, Committee Chair
Bounding maximum stack depth for embedded system applications is essential in order to avoid conditions such as stack overflow. Stack usage information is useful for allocating the stack into a memory hierarchy. Prior work in stack space analysis addresses specific issues such as handling interrupts and target ISAs other than ARM. In this thesis, we propose a methodology for stack space analysis based on euler tour traversal of the call graph to determine the maximum stack depth of the application, good preemption points for tasks and hotspots in stack depth. Our main contribution is Astute (A STack UTilization Estimator), a tool that implements our methodology for stack space analysis of ARM executables. We also study the effects of compiler optimization on maximum stack depth of an embedded system application and benchmark programs.
STI Concepts for Bit-Bang Communication Protocols
(2003-01-28) Kumar, Nagendra J; Dr. Thomas M. Conte, Committee Member; Dr. Eric Rotenberg, Committee Member; Dr. Alexander Dean, Committee Chair
In the modern times, embedded communication networks are being used in increased number of embedded systems to provide more reliability and cost effectiveness. Designers are forced to limit and minimize the size, weight, power consumption, costs and also the design time of their products. However, network controller chips are also expensive and hence moving functionality from hardware to software cuts down the costs and also makes custom fit protocols easier to implement. Traditional methods of sharing a processor are not adequate for implementing communication protocol controllers in software because of the processing required during each bit. The available idle time is fine grain compared to the bit time and is usually small for even the fast context switching techniques (e.g. co-routines) to run any other thread. Without some scheme to recover this fine-grain idle time, no other work in the system would make any progress. Software Thread Integration (STI) provides low cost concurrency on general-purpose microprocessors by interleaving multiple threads of control (having real-time constraints) into one. This thesis introduces new methods for implementing communication protocols in software using statically scheduled co-routines and software thread integration. With co-routines, switching from primary to secondary threads and vice versa can be done without incurring a penalty as severe as "context - switching". This technique will be been demonstrated on the SAE J1850 communication standard used in off- and on-road land-based vehicles. These methods also minimize the number of co-routine calls needed to share the processor thereby enabling finer-grain idle time to be recovered for use by the secondary thread. Increased number of compute cycles implies ∗Improved performance of the secondary thread and ∗Reduced minimum clock speed for the microprocessor. Thus, now more secondary thread work can be done and also the minimum clock speed required of the processor is reduced. These factors enable the embedded system designers to use processors more efficiently and also with less development effort.
STI Friendly Clock Recovery Techniques for Bit Banged Communication Protocols
(2004-05-19) Thirumoolan, Sudhagar; Dr. Alexander Dean, Committee Chair; Dr. Frank Mueller, Committee Co-Chair; Dr. Vincent Freeh, Committee Member
Nowadays embedded communication networks are used in a number of applications. A majority of these networks use a shared medium for communication. Controllers for these shared medium protocols can be implemented in hardware or software. Protocol implementations in software using standard off the shelf microcontrollers have been found to be faster, easier and most cost effective. In an embedded communication network, it is essential that the protocol controllers are in synchrony with each other. A slight phase difference between the clocks of the protocol controllers can lead to errors in the data propagated between them. If the sender has a slight error in its clock frequency the receivers that are reading a message from the sender need to adapt to the clock of the sender by recovering the clock information from the data on the shared medium. This paper talks about the various existing techniques in hardware and software and compares a few proposed clock recovery techniques which can be used for software protocol implementations using STI. A good clock recovery technique must adapt to the sender as quickly as possible and maintain very little phase difference with the sender. It must consume very few computational cycles and the code blocks must remain as close together as possible to avoid fragmenting the idle time of the protocol implementation. In order to facilitate STI, a good primary thread implementation will need to have large chunks of idle time which can be merged with useful code from a secondary thread. It is also required that the primary thread should have fixed or almost fixed execution times for all its functions, in order to be able to recover as much idle time as possible. The proposed techniques have large chunks of idle time as well as try to catch up with the sender's clock as quickly as possible. Hence they are good candidates for being used in software protocol implementations using STI. However, the limitation of these techniques is the fixed number of cycles up to which they can recover in every bit interval when the receiver's clock is slower than the sender's.