Browsing by Author "Dr. Alexander G. Dean, Committee Chair"

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    Relaxing Control Flow Constraints in ASTI
    (2003-07-29) Asokan, Vasanth; Dr. Alexander G. Dean, Committee Chair; Dr. Frank W. Mueller, Committee Co-Chair; Dr. Mihail Sichitu, Committee Member
    Asynchronous Software Thread Integration (ASTI) provides methods to reclaim sub-bit duration idle intervals in the real-time threads which bang bits onto and off from the network bus, by allowing asynchronous progress of secondary threads. Current ASTI techniques constrain the secondary thread from having procedures and procedure calls because of conflicts in timing that arise. Constraining procedure calls is very inelegant and limits the usefulness of the techniques developed in ASTI. It also significantly lowers the ease with which software can be developed and maintained. Flat code is significantly larger in size compared to code that has been structured into procedures. This can be extremely important in embedded systems where code memory is at a premium. This thesis presents a novel application of the traditional compiler optimization techniques - procedure inlining and procedure cloning, to remove the constraints on procedure calls with ASTI. Under the assumption that the system cannot tolerate the inlining of all procedure calls, this thesis provides an algorithmic approach to choosing some subset of calls to inline and to remove the timing conflicts in the remaining procedures in the most optimal fashion. Timing conflicts in the remaining calls can be removed by padding calls to a procedure to the worst case. Procedure cloning can be used to extend this by clustering calls that have similar environments together and dedicating a clone of the procedure to the cluster. We show that this would result in significant reductions not only in the amount of static padding cycles required, but also in the amount executed at run-time too. We expect a secondary thread, which uses cloning to reduce the amount of padding, to show a significant speedup when compared to a non-cloned version. Providing a scientific approach for constraint relaxation, instead of an ad-hoc one, will also produce much more efficient code both in terms of size and consumed processor cycles
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    A Simulator for Microcontroller-based Underwater Ultrasonic Communications
    (2006-08-04) Govilkar, Samir Rajshekhar; Dr. Mihail L. Sichitiu, Committee Member; Dr. Alexander G. Dean, Committee Chair; Dr. Suleyman Sair, Committee Member
    The aim of this thesis is to aid in the development of the RAPTEX project. The RAPTEX project deals with designing efficient communication protocols for underwater telemetry and sensor networks. Underwater telemetry is used to track crabs, initially in shallow water and later in marine environments. Ultrasonic waves are used for such underwater telemetry. The ultrasonic waves are affected by various phenomena as they pass through water. These phenomena include attenuation, multi-path fading, noise, etc. A small microcontroller based transmitter will be placed on the back of the crab allowing the telemetry data to be transmitted. The microcontroller will directly drive an ultrasonic transducer through a Digital to Analog Converter to output a modulated carrier wave. It is necessary to simulate the communication between the microcontroller based transmitter and the receiver before testing this system in the real-world environment. The purpose of the simulation is two-fold. It helps to validate the design and it also helps in verifying the end-to-end communication of the system. This becomes important as more and more higher layer protocols are added to the RAPTEX project. Since the simulation environment has control over all the parts of the communication system; viz. the transmitter (based on the AVR microcontroller), the channel and the receiver, it is possible to inspect the flow of data at any point by adding suitable taps.
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    Software Thread Integration for Instruction Level Parallelism
    (2007-07-05) So, Won; Dr. Eric Rotenberg, Committee Member; Dr. Thomas M. Conte, Committee Member; Dr. Vincent W. Freeh, Committee Member; Dr. Alexander G. Dean, Committee Chair
    Multimedia applications require a significantly higher level of performance than previous workloads of embedded systems. They have driven digital signal processor (DSP) makers to adopt high-performance architectures like VLIW (Very-Long Instruction Word) or EPIC (Explicitly Parallel Instruction Computing). Despite many efforts to exploit instruction-level parallelism (ILP) in the application, the speed is a fraction of what it could be, limited by the difficulty of finding enough independent instructions to keep all of the processor's functional units busy. This dissertation proposes Software Thread Integration (STI) for Instruction Level Parallelism. STI is a software technique for interleaving multiple threads of control into a single implicitly multithreaded one. We use STI to improve the performance on ILP processors by merging parallel procedures into one, increasing the compiler's scope and hence allowing it to create a more efficient instruction schedule. STI is essentially procedure jamming with intraprocedural code motion transformations which allow arbitrary alignment of instructions or code regions. This alignment enables code to be moved to use available execution resources better and improve the execution schedule. Parallel procedures are identified by the programmer with either annotations in conventional procedural languages or graph analysis for stream coarse-grain dataflow programming languages. We use the method of procedure cloning and integration for improving program run-time performance by integrating parallel procedures via STI. This defines a new way of converting parallelism at the thread level to the instruction level. With filter integration we apply STI for streaming applications, exploiting explicit coarse-grain dataflow information expressed by stream programming languages. During integration of threads, various STI code transformations are applied in order to maximize the ILP and reconcile control flow differences between two threads. Different transformations are selectively applied according to the control structure and the ILP characteristics of the code, driven by interactions with software pipelining. This approach effectively combines ILP-improving code transformations with instruction scheduling techniques so that they complement each other. Code transformations involve code motion as well as loop transformations such as loop jamming, unrolling, splitting, and peeling. We propose a methodology for efficiently finding the best integration scenario among all possibilities. We quantitatively estimate the performance impact of integration, allowing various integration scenarios to be compared and ranked via profitability analysis. The estimated profitability is verified and corrected by an iterative compilation approach, compensating for possible estimation inaccuracy. Our modeling methods combined with limited compilation quickly find the best integration scenario without requiring exhaustive integration. The proposed methods are automated by the STI for ILP Tool Chain targeting Texas Instrument C6x VLIW DSPs. This work contributes to the definition of an alternative development path for DSP applications. We seek to provide efficient compilation of C or C-like languages with a small amount of additional high-level dataflow information targeting popular and practical VLIW DSP platforms, reducing the need for extensive manual C and assembly code optimization and tuning.