Browsing by Author "Dr. Edward F. Gehringer, Committee Chair"

Now showing 1 - 3 of 3

Expertiza as a Support System for Collaborative Learning
(2008-04-21) Wesley, Ravinand Isaac; Dr. Edward F. Gehringer, Committee Chair; Thomas L. Honeycutt, Committee Member; Laurie A. Williams, Committee Member
Page Pinning Improves Performance of Generational Garbage Collection
(2006-05-04) Sawyer, Richard Kevin; Dr. Edward F. Gehringer, Committee Chair; Dr. Gregory T. Byrd, Committee Member; Dr. Suleyman Sair, Committee Member
Garbage collection became widely used with the growing popularity of the Java programming language. For garbage-collected programs, memory latency is an important performance factor. Thus, a reduction in the cache miss rate will boost performance. In most programs, the majority of references are to newly allocated objects (the nursery). This work evaluates a page-mapping strategy that pins the nursery in a portion of the L2 cache. Pinning maps nursery pages in a way that prevents conflict misses for them, but increases the number of conflict misses for other objects. Cache performance is measured by the miss-rate improvement and speedup obtained by pinning on the SPECjvm98 and the DaCapo benchmarks. Pinning is shown to produce a lower global miss rate than competing virtual-memory mapping strategies, such as page coloring and bin hopping. This improvement in miss rate shortens overall execution time for practically every benchmark and every configuration. Pinning greatly reduces average pause time and variability of pause times for nursery collections.
Performance Comparison of Software Transactional Memory Implementations
(2007-07-09) Kariath, Riya Raju; Dr. Yan Solihin, Committee Member; Dr. Edward F. Gehringer, Committee Chair; Dr. Xiaosong Ma, Committee Member
Software Transactional Memory (STM), an optimistic concurrency control mechanism for controlling accesses to shared memory, is a promising alternative to lock-based mutual exclusion strategies. A transaction in this context is each piece of code that executes indivisibly in a shared memory region. Like database transactions, STM transactions preserve linearizability and atomicity properties. This thesis project presents performance comparisons based on memory, indirection and compute overheads of different STM implementations. More precisely, it compares three STM systems — a non-blocking STM due to Fraser (FSTM), a lock-based STM due to Ennals, and a lock-based STM (TL2) with global version-clock validation due to Dice et.al. A comparison employing diverse classes of STMs helps in a deeper understanding of various design choices and potential trade-offs involved. In particular, suitability of an STM is analyzed versus another STM in a given scenario. The empirical evaluations done as part of this thesis conclude that Ennals' STM has an edge over TL2 and FSTM, as it performs consistently well on low and high contention settings. The results also suggest that lock-based STMs use less memory than lock-free STMs due to better cache locality.