Browsing by Author "Dr. Mesut Baran, Committee Member"

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Design and implementation of a Digital Controller for High Power Converters
(2008-11-11) Mundkur, Sameer Shailesh; Dr. Alex Q. Huang, Committee Chair; Dr. Mesut Baran, Committee Member; Dr. Subhashish Bhattacharya, Committee Member
Multi-level converter topologies are widely used in utility power electronics as it offers improved reliability, multiple layers of protection, flexibility of expansion and isolation. This thesis proposes to design and implement a distributed control topology for high power electronics which consists of centralized controller which would process various power electronic related signals like voltage, current, switching device temperatures as well as several localized controllers which communicate with the central controller and generate gate drive signals for each high power switching device/ bridge converter. So there is essentially a two layer hierarchy â€“ the complex digital signal processing and modulation algorithms are done at the central controller level and the switching modulation signals are then sent to several localized controllers which then process this data and control the power electronics. The central controller provides the supervisory control while the actual device level control is delegated to several local controllers. This topology provides flexibility as well as a robust communication scheme between controllers. This thesis also looks at a shared control algorithm computation approach by moving some of the computation from the DSP to the FPGA for faster processing and generation of gate drive control. This implementation of an intelligent modular controller would result in better performance and fault-response time through the exploitation of parallelism inherent in a programmable hardware based controller approach. The design will be captured using verilog HDL and synthesized on a FPGA.
Digital Controller Design for Cascaded-Multilevel-Converter Based STATCOM Systems
(2007-02-26) Yang, Zhaoning; Dr. Mo-Yuen Chow, Committee Member; Dr. Mesut Baran, Committee Member; Dr. Alex Q. Huang, Committee Chair
The purpose of the research has been to develop digital controllers for the Cascaded-Multilevel-Converter based STATCOM systems. STATCOM is one of the most important shunt FACTS controllers, which is designed to support the voltage and improve stability of the power system. Cascaded Multilevel Converter (CMC) is increasingly used at high power area due to its direct high voltage output with no need of transformer, which makes it as a good topology for STATCOM. Also because of the identical structure of each cell (H-bridge), CMC is the best candidate to be modularized. In this thesis, two different digital controller developments are presented. First digital controller has conventional centralized controller structure. It uses a DSP plus FPGA as central controller. The DSP performs the control functions while FPGA is behaving like a bridge between DSP and peripheral devices. This topology is widely used in industry due to its simple and straightforward structure. Off-line simulation and hardware-in-the-loop real-time simulations are carried out to verify the design. Based on this topology a digital controller system has been developed and implemented in a three level STATCOM system. However, the conventional centralized controller has some disadvantages. The central controller has direct connections with all converters. For high voltage and power rating converters, it is true that the power converters will consist of many modular blocks and these blocks will be placed at some distance from the controller. In this case, digital switch signals must be sent to the converters via optical fiber to improve reliability. However, the required fiber connections are too many that increase cost and the risk of fault. Moreover, the analog signals from the sensors such as the voltage and current are usually sending back to the central controller through analog wire connections that has low electromagnetic interference (EMI) susceptibility. To solve these problems, a modular digital controller topology is proposed. It has one central controller plus multiple local controllers. Every module converter has its own local controller which is placed very close to the modular converter. The local controller work as a "brain" for the converter. This "brain" realizes all the sensor signals of the module converter and sends them to central controller via asynchronous series communication protocol. Central controller performs the close loop algorithm and generates switching states. These switching states are sent to local controllers also through asynchronous series communication protocol. All the long distance data transmission is through optical links, which greatly increase the EMI susceptibility. The number of the fibers is reduced due to the series communication protocol. This modular controller is a little bit more complicated than the conventional centralized structure. But it can truly achieve "modularization", which means improved reliability, isolation and increased expansion flexibility. This modular controller is built and verified through 50V 5A experiments.
Thermal Design and Optimization of Parasitics for High Power Converters
(2008-11-18) Doss, Shoubhik Ravindranath; Dr. Alex Q. Huang, Committee Chair; Dr. Subhashish Bhattacharya, Committee Co-Chair; Dr. Mesut Baran, Committee Member
Design of high power converters require deep insight into magnetic, thermal and mechanical parameters of the converter, besides the electrical parameters, for it to function in a desired manner. The high power converters have losses proportional to their power rating; even a highly efficient converter (98%) could have losses as high as >100 kW. It is essential to extract this thermal energy form the system so that the components in the converter do not fail. Extraction of such large quantities of thermal energy is a formidable challenge and has been dealt with in detail in this work. Various options for this process have been discussed. Optimization of the interconnecting bus-bar network in the converter is another important aspect of the design. Minimization of stray inductances and loops lead to lower voltage stresses on the semiconductor devices and proper operation of the converter. Imperfect joints between interconnecting bus-bars form stray resistances which lead to localized heating of the bus-bars. This thermal cycling leads to faulty joints, causing inefficient operation of the converter. To maximize the efficiency of the converter, such interconnection issues have been addressed. Finally, the weight distribution, foot-print and volume of the converter play a key role in its manufacturability and marketability. Special attention has been given to the materials selected in the design process to maximize the life of the converter and ensure correct operation under different ambient temperatures and weather conditions. A well built converter must follow the guidelines laid by the mechanical and thermal aspects of the design process.