Browsing by Author "Dr. Michael Steer, Committee Member"

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    Inductively Coupled Connectors
    (2009-03-04) Chandrasekar, Karthik; Dr.Paul Franzon, Committee Chair; Dr. Michael Steer, Committee Member; Dr. Gianlucca Lazzi, Committee Member; Dr. J.P Maria, Committee Member
    CHANDRASEKAR, KARTHIK. INDUCTIVELY COUPLED CONNECTORS (under the direction of Dr. Paul Franzon) AC coupled interconnects show promise to enable multi-gigabit/second data rates between high pin count IC’s within a multi-chip module, while achieving significant power savings as well [3]. AC Coupling can be realized with planar inductive or capacitive elements. Inductive coupling offers many degrees of freedom for system design by varying geometric parameters to tune parasitic elements in the model, such as: the crossover capacitance between the spirals, the magnetic coupling coefficient, winding resistance, inductance ratio and impedance terminations. So far, inductively coupled interconnects have mainly shown potential for multi-Gbps signaling only in level 1 interconnections, i.e. direct chip to chip communication and 3D IC’s. Multi-Gbps pulse signaling is demonstrated with inductively coupled interconnects across packaging interfaces in this dissertation. This shows feasibility of realizing sub-mm pitch, true Zero Insertion Force (ZIF) surface mount connectors and sockets (i.e. level 2 and level 3 interconnections). Inductors are fabricated on two opposing surfaces, e.g. the faces of a connector or socket. When mated, they form a transformer, which is used to carry signals through the mated interface. The main advantage of building a separable connection this way, is that it is possible to achieve a high density with a simple mechanical structure. This in turn, offers potential for cost reduction and support for true three dimensional packaging. Being a true zero-insertion force interface, very high pin counts could be easily supported. ZIF sub-mm pitch surface mount inductive connector technology also addresses some of the signal integrity problems inherent in pressfit style connectors. It is difficult to use capacitive coupling for this application, because the structure is placed in the transmission line, not at one end. Thus both the driving impedance and load being driven is 50 ohms. The high, frequency-dependent impedance of a series capacitor would lead to reflection noise (i.e. return loss). Unless large capacitors or lossy codes guaranteeing only high frequency content are used, the transmitted swing would be too small (i.e. excessive insertion loss). In contrast, inductively coupled connectors can achieve broad band matching impedance and give acceptable values to return and insertion losses. Methods to optimize signal integrity are discussed in detail for inductively coupled systems in this dissertation. The signaling data rate achieved in this system is from 1 Gbps to 8.5 Gbps, which depends on the 3 dB coupling frequency of the composite channel consisting of the inductive interconnections and the transmission lines.
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    Inductively Coupled Interconnect for Chip to Chip Communication over Transmission Line
    (2009-05-20) Shah, Chintan Hemendra; Dr. Paul Franzon, Committee Chair; Dr. Kevin Gard, Committee Member; Dr. Michael Steer, Committee Member
    As data frequency increases beyond several Gbps range, low power chip to chip communication becomes more critical. The concept researched in this thesis is inductively coupled interconnect (LCI) over short length transmission line. The data will be transmitted across a 10 cm differential microstrip line on FR-4 material with a transformer on each side of the line. The transmitter and receiver circuits are designed in TSMC 0.18μm process technology and can operate at 2.5 Gbps. The power consumption of the design is 5.53 mW at 2.5 Gbps which yields around 2.21 mW.Gb-1.s-1. This design can achieve BER of less than 10-12. The inductive coupling will reduce DC power because the low frequency DC component of the signal will be blocked by coupling inductors. The power consumed by this design is lower than most of the conventional I/Os that use physical contact interconnects. An H-bridge current steering driver is used at the transmitter and a differential amplifier and Sense-amp Flip flop is used at the receiver.
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    RF pHEMT Switch Model for Multiband Cell Phone Circuits
    (2004-11-05) Jasper, David Brian; Dr. Leda Lunardi, Committee Member; Dr. Michael Steer, Committee Member; Dr. Douglas Barlage, Committee Chair
    Simulation of Radio Frequency Switches used in the cellular phone industry is the main focus of this study. The RF pHEMT's used in an antenna switch for multiband cell phone circuits requires the use of an accurate model during simulation of the RF system. The pHEMT model extracted in this study utilizes theoretical methods within the extraction software and an analysis of simulated data and measured data. This study describes the techniques of calibration, model extraction, and data analysis.
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    A Scalable Architecture For Hardware Acceleration of Large Sparse Matrix Calculations
    (2007-08-01) Hamlett, Matthew Issiah; Dr. Paul Franzon, Committee Chair; Dr. Gianluca Lazzi, Committee Member; Dr. Michael Steer, Committee Member
    The task of implementing the Jacobi method has been looked at from several research works over the years. The Jacobi method is considered the most ideal Iterative method for implementation on FPGAs because of its inherent parallelism and lack of data dependencies. In this work, we look specifically at solving very large matrix equations in the form of Ax = b. Here A is a sparse matrix with dimensions of 1 million x 1 million with 6 entries per row. X is the vector we are solving for, and b is a known vector. All data is in 64-bit IEEE-754 floating point format. Previous work in this area has implemented the Jacobi method using only on chip memory accesses, greatly limiting the size of the matricies that can be solved. By using external memory, we present a design that is practical and can be used to accelerate various engineering and scientific problems today. In this design, we also implement the resources necessary for Multiple FPGAs to be used in a distributive manner so as to tackle larger problems. Our design gives a peak floating point performance of 1.8 GFLOPS and a sustained floating point performance of 1.18 GFLOPS. This is a speed up factor of around 2.95 when compared to the sustained performance that is typically seen on today's general purpose computers with this type of problem. To obtain this high peak floating point performance, we present in this paper a group of memory interfaces that are capable of supplying a total data rate of 20 Gb/sec sustained.