Browsing by Author "Dr. Paul D. Franzon, Committee Chair"

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Design and Fabrication of a MEMS Pressure Sensor and Developing a Release Protocol for MEMS
(2002-08-28) Bhate, Kaustubh Ramesh; Dr. Paul D. Franzon, Committee Chair; Dr. Christine S. Grant, Committee Co-Chair; Dr. Griff Bilbro, Committee Member
This presents the design and fabrication of a MEMS Pressure Sensor for application in the Textile Industry. The transducer element in the sensor is a piezoresistive device. The Pressure Sensor layout is made in Cadence-Virtuoso and a 3-D Model is simulated in MEMCAD. Calculated and simulated results are compared. Processing steps are carried out in the NCSU Cleanroom to fabricate the device. A part of this thesis also attempts to develop a Release Protocol for MEMS devices made in the SUMMIT process. SUMMIT chips are released by wet etching in HF followed by rinsing in Methanol. The released device is then observed under Optical Microscope for results. Cantilever beams are also designed in SUMMIT process to be tested electrically when they come back after being fabricated at Sandia National Laboratories.
Design Flow Based on Sensitivity Analysis for High-speed Digital Circuits
(2004-04-08) Morgan, Andrew Stacy; Dr. W. Rhett Davis, Committee Member; Dr. Paul D. Franzon, Committee Chair; Dr. Griff Bilbro, Committee Member
The purpose of this work is to develop a design flow for high-speed digital circuits that may be used to increase the quality of circuit performance and improve the ability of inexperienced circuit designers. This design flow meshes the use of hand and simulation analysis to increase intuitive understanding of the dominant relationships and most significant circuit parameters that determine performance. The research relies heavily on determining the sensitivity of chosen performance measures to variation in selected circuit parameters, such as transistor gate width. Four detailed examples that follow the generalized design flow are included to illustrate practical application. The examples consist of the following circuits: source-follower, gate-isolated voltage sense-amplifier, Schmidt trigger, and dual-rail domino logic gate. The examples include design specifications, topology advantages and disadvantages, a suggested design approach, and detailed sensitivity analysis including quantitative simulation results supporting drawn conclusions.
Design of DDR2 Interface for Tezzaron TSC8200A Octopus Memory intended for Chip Stacking Applications
(2010-05-14) Bapat, Ojas Ashok; Dr. W. Rhett Davis, Committee Member; Dr. Eric Rotenberg, Committee Member; Dr. Paul D. Franzon, Committee Chair
This document talks about the design of a DDR2 Controller for the Tezzaron TSC8200A (Octopus) High-Speed Self-Repairing L3 Memory which is intended for chip stacking applications. The controller is the part of a LEON3 processor architecture. The system consists of three leon processor cores connected to all the peripherals and memory through an AMBA-2.0AHB/APB Master/Slave bus interface. The development environment is the gaisler open source library which is a set of reusable IP cores designed for system on chip development. The advantage of using this environment is that the libraries are technology independent and can be used with various target technologies and CAD tools. The DDR2 controller acts as a slave to the AHB bus. On the other side is the Tezzaron Octopus Memory. The controller consists mainly of two parts; one which implements the state machines for both the AHB side interface and the Memory side interface and the other which does the job of shifting, alignment and conversion of signals from single to double data rate. This part also has the pads instantiated in it. As the Octopus Memory has two independent ports which are seen as two separate parallel memories by the host processor, we have two instantiations of the controller in the design. Also, unlike conventional DDR2 standards, the Octopus Memory uses only single ended signals. Also, since this memory has been specially designed for stacking, it does not support/require on-die termination and off-chip driver capability. Here, we talk about the challenges faced in the design of the Controller state machines, the physical interface, synthesis and the functional and timing verification of the DDR2 controller. Also, we talk about the place and route strategy adopted to layout the entire 3-core processor architecture along with the controller and memory. Since the Tezzaron Octopus memory IP was not available at the time, we have used a dummy .lef block for it. Assertion based formal verification techniques were used the verify the outputs and internal signals of the controller. The design was synthesized in IBM 130nm technology library with artisan memories and I/O pads. The total synthesized area of the entire user logic is 7.01 mm2 without the macros and pads. The standard cell area for just the controller is 4.89 mm2 . The total die size for the user logic with the macros and pads is 7mm x 7mm with a core utilization of 0.7. Having memory on a separate die helps us get all the benefits of an on chip memory while reducing the complexity and number of process steps. The memory and the user logic can be can be individually processed in different feature sizes or even different materials. The dies can be than stacked on top of each other and connected with through silicon vias. The Octopus memory follows the IMIS interface specification which defines a high bandwidth 1024-bit wide vertical bus at the memory surface. This allows for shorter interconnects, thus greatly reducing the latency. It improves the bandwidth by allowing up to eight parallel 64 bit double pumped data ports.
Development of ASIC Technology Library for the TSMC 0.25 micrometers Standard Cell Library
(2003-08-19) Sundararaman, Vishwanath; Dr. Griff Bilbro, Committee Member; Dr. Eric Rotenberg, Committee Member; Dr. Paul D. Franzon, Committee Chair
The Synopsys synthesis tool generates the hierarchical netlist of a design using worst-case and best-case ASIC technology libraries. The worst-case library checks for the setup time violation and the best-case library checks for the hold time violations of the design. The worst-case library is characterized by a supply voltage of 2.25V, operating temperature of 125°C, and slow process corner. The best-case library is characterized by a supply voltage of 2.75V, operating temperature of -55°C, and fast process corner. The technology libraries are developed for the CMOS TSMC 0.25μm technology. The CMOS nonlinear delay models are used for delay calculations. Variations in operating temperature, supply voltage and manufacturing process causes performance variations in electronic networks. Using different operating conditions, the timing of the design under different environmental conditions can be evaluated. The delay values specified in the cells for a technology specify a set of nominal operating condition. The worst-case and best-case libraries are developed by running HSPICE simulations for all the 36 basic cells. The technology library contains information used for the following synthesis activities: • Translation — functional information for each cell • Optimization — area and timing information for each cell (including timing constraints on sequential cells) • Design rule fixing — design rule constraints on cells
Forwarding Engine for IPv6
(2003-06-03) Sawhney, Ishdeep Singh; Dr. Gregory T. Byrd, Committee Member; Dr. Yannis Viniotis, Committee Member; Dr. Paul D. Franzon, Committee Chair
We focus on forwarding engine for million entry IPv6 (Internet Protocol version 6) routing tables. The memory requirements are analyzed for a trie based scheme and a binary search scheme for doing IP address lookup. We also develop an architecture to bound the worst-case update performance of lookup schemes. The scalability of the two lookup schemes was analyzed with respect to increasing routing table size and increase in address size. Currently available DRAM memories were analyzed for memory access requirements and memory mapping schemes were developed to improve the lookup performance. The trie based scheme was analyzed with respect to variations in different parameters like depth, pipeline stages, etc. The update performance of IP lookup schemes was identified as a potential problem and an architecture was developed to bound the worst-case performance. The update mechanism is independent of the lookup scheme and is implemented in hardware. The implementation is done in a 0.25u CMOS cell library.
FPGA Implementation of a Low Power Doppler Invariant BFSK Receiver
(2003-09-03) Arkesh, Vikram; Dr. J Keith Townsend, Committee Member; Dr. Paul D. Franzon, Committee Chair; Dr. Rhett Davis, Committee Member
A non coherent frequency shift keying (FSK) receiver architecture is designed potentially for low power applications. The receiver incorporates a 16 point Fast Fourier Transform (FFT) for symbol detection and can withstand large Doppler shifts. Almost all the design units of the receiver are digital designs for better power efficiency and reliability. The receiver functions on one bit data processing and supports data rates of 10kbps, 1kbps and 100bps. Co-ordinate rotation (CORDIC) algorithm is used for complex multiplications while computing FFT, evading the use of power hungry multipliers. The design and simulation of the receiver is carried out in MATLAB/SIMULINK. The MATLAB model is translated to a XILINX FPGA hardware model using system generation features of the XILINX development system. The hardware model is synthesized to a virtex-2 XILINX FPGA and various performance parameters are extracted. A control system for symbol and timing detection is designed and modeled in VHDL, synthesized to XILINX hardware and interfaced to the receiver.
Hardware Realization and Implementation Issues for the Sliding-window Packet Switch
(2006-04-16) Phelps, Brian Roberson; Dr. Arne A. Nilsson, Committee Member; Dr. Thomas M. Conte, Committee Member; Dr. Paul D. Franzon, Committee Chair; Dr. Sanjeev Kumar, Committee Member
Shared memory packet switches are known to provide the best delay-throughput and respond well to bursty traffic. Shared memory switches are also known to scale poorly due to centralized control and memory bottlenecks. The Sliding Window Packet Switch (SW) algorithm is a shared memory switch that employs decentralized control and multiple memory modules to facilitate the scalability of hardware. The SW algorithm is independent of the type of packet or cell. This research has two closely related goals. The first goal is to implement the SW algorithm in hardware such as an FPGA. This implementation is actually a specific case of the SW algorithm with four input ports and four output ports (i.e. a 4x4 switch). The second goal is to determine what scalability constraints exist in hardware for larger numbers of input and output ports (large NxN). These constraints are used to predict the overall throughput that the hardware implementation can handle.
Instruction Cache Checkpoints Using Phase Tracking and Prediction
(2005-12-30) Mukundan, Janani; Dr. Edward Davis, Committee Member; Dr. Vincent Freeh, Committee Member; Dr. Paul D. Franzon, Committee Chair
The Memory wall is standing taller than ever. There is an ever growing imbalance between memory bandwidth and processor speeds. Due to these diverging rates most applications are limited by memory performance. Various aggressive techniques to hide memory latency have done little to hide this gap. Clearly, we will need better optimization techniques to bridge the gap between processor and memory speeds. In future it will be necessary for us to understand program patterns and behavior at run time, so that we can efficiently utilize various optimization techniques. Past research [10] has suggested that program's tend to have cyclic patterns of execution. They tend to execute in phases, which repeat over time. It is possible to efficiently capture, classify and predict phase based program behavior at run time [13]. We propose using Phase Tracking and Prediction to bridge the memory gap. We introduce the concept of Instruction Cache Checkpoints that exploit program behavior to prefetch into the Instruction Cache. The intuition behind this scheme is that since phase behavior can be predicted, we can effectively pre-fetch instructions according to phase transitions. We also propose a new improved Phase Prediction architecture based on phase run-lengths. We begin by studying and evaluating phase behavior in SPEC2k FP benchmarks. The observed phase behavior is then exploited by creating Instruction Cache Checkpoints that use prefetching based on phase changes. Detailed simulation of five of the SPEC 2k FP benchmarks show that using Instruction Cache Checkpoints gives us an average reduction of 17.8% in the number of Instruction Cache misses.
Optical Hardware Tradeoffs for All Optical Multicast
(2002-07-12) Chandrasekar, Karthik; Dr. Paul D. Franzon, Committee Chair; Dr. John Muth, Committee Member; Dr. Zhibo Zhang, Committee Member
All Optical WDM Networks are fast becoming the natural choice for future backbones and in order to meet the exponentially increasing traffic demands, it would be beneficial to support all optical multicast. One way to support multicast is to provide optical splitters at various switching nodes along the network. The main contribution of this thesis is in demonstrating that all optical multicast can be made practical for both 1:2 splitters and 1:N splitters through the proper incorporation of in-line EDFA's and other optical hardware components available off the shelf. Using electronics for 3-R regeneration at the intermediate nodes is costly and hence our model uses EDFA's. Most previous work in this direction has addressed multicast feasibility from an architectural standpoint while this thesis discusses issues from a physical designer's perspective. An All Optical CAD simulation tool from Virtual Photonics was used to simulate a variety of multicast networks taking into account relevant Nonlinear effects such as chromatic dispersion, four wave mixing, stimulated Raman scattering and all phenomena commonly encountered in Cascaded EDFA chains such as Accumulated Spontaneous emission noise, SNR Transients and Gain Saturation.
Planar Edge Defined Alternate Layer Process (PEDAL) - An Unconventional Technique for Fabricatinon of Wafer Scale Sub-25 nm Nanowires and Nanowire Template
(2006-12-08) Sonkusale, Sachin Ramrao; Dr. Mark Johnson, Committee Member; Dr. Veena Misra, Committee Member; Dr. Gerald Iafrate, Committee Member; Dr. Paul D. Franzon, Committee Chair
As defined by the US national science foundation, "nanofabrication is the process of making functional structures with arbitrary patterns having minimum dimensions less than 100 nm". Nanofabrication, a key step in nanotechnology, has applications not only in conventional semiconductor devices but also in sensors, memory, nanofluidics, cross-bar logic architecture and nanoelectrical mechanical systems. In this research I have proposed and successfully demonstrated an unconventional lithographic technique called Planar Edge Defined Alternate Layer (PEDAL) to fabricate wafer scale sub 25 nm nanowire template. Good dimensional control and wafer scale uniformity of this process is shown by uniformity analysis of the width and spacing of an array of sixteen line-width structures with approximately 42 nm pitch and twenty four line-width structures with approximately 23 nm pitch. Results on routing capability of this process along with results of palladium nanowires obtained by PEDAL lift-off process done on the template with 42 nm pitch is also reported. In the case of template with array of sixteen lines, the average pitch of array across the 4 inch wafer was measured to be 40.83 nm with the standard deviation of 2.29 nm where as the average pitch of the lines in an array was found to be 41.5 nm with the standard deviation of 4.64 nm. After Pd lift-off the average pitch in nanowire array was measured to be 41.88 nm with standard deviation of 1.83 nm, close to the values obtained for the template. In the case of array of twenty four line-widths, average pitch of array across the 4 inch wafer was measured to be 21.1 nm with the standard deviation of 5 A where as the average pitch of the line in an array was found to be 22.6 nm with the standard deviation of 9 A. Other than experimental analysis, results from numerical simulations to find processing conditions to get good dimensional control in PEDAL process by taking process variations into account are also presented in this thesis.