Browsing by Author "Dr. Paul Franzon, Committee Chair"

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Adding Scalability to IBIS by Using AMS Languages
(2006-05-04) Fernando, Paul; Dr. Paul Franzon, Committee Chair; Dr. Kevin Gard, Committee Member; Dr. Rhett Davis, Committee Member
From 1993 to about 1998, IBIS remained THE digital IO buffer model format. But as the operating frequencies & complexity of I/O buffers increased, IBIS has been left behind in favor of SPICE models, since IBIS is inaccurate or unable to model these advanced buffers. This trend brings the industry back toward a single EDA vendor solution, which is what IBIS was designed to prevent. In an effort to relinquish these shortcomings, multi-lingual model extensions were added to IBIS Version 4.1. Specifically: Berkeley-SPICE, VHDL-AMS and Verilog-AMS files. These extensions in IBIS 4.1 give IBIS practically unlimited behavioral and structural modeling capabilities as well as more accuracy. The problem is that the AMS languages have been slow in making their way into SI tools and the SI community; mainly due to the associated learning curve, since AMS is relatively new to the SI world. The solution was to build an AMS library of tool independent basic elements ('element library') and a separate 'template library' which would contain the models of complex buffers (Pre-emphasis, LVDS, DDR2 etc). The templates would be created by instancing elements from the 'element library'. An IBIS to AMS converter would convert conventional IBIS files into AMS format and provide the data for the template. The IBIS macro-modeling committee was created in July 2005 with these main goals in mind. This thesis deals with the new AMS macro-modeling methodology put forth by the IBIS macro-modeling committee and the contributions I made to it as its only student member. My specific contribution was the IBIS to AMS (ibis2ams) converter tool. The thesis also presents the updates I made to the IBIS plotting utility (s2iplt) and the spice to IBIS toolkit (s2ibis). All tools are publicly available on the NCSU ERL website.
Design of Fully Integrated Wireless CMOS MEMS Device for Intraocular Pressure Measurement
(2008-05-10) Anigulu Mohan, Deepak Kumar; Dr. Kevin gard, Committee Member; Dr. M.K.Ramasubramanian, Committee Co-Chair; Dr. Paul Franzon, Committee Chair
The thesis research presented here explores the design and fabrication of wireless Integrated CMOS MEMS device for continuous intraocular pressure measurement. A complete study of the existing solutions for sensing intraocular pressure is made and the problems involved in them are identified in the report. A simple, low power, less invasive solution for the application is then proposed. Electromagnetic modeling of the inductive link is done and optimum dimensions for the antenna are finally suggested. Complete design of all the components of the system such as control circuit, power conversion and conditioning circuits, reference circuits necessary for the reliable functioning of the device is presented. Integration of MEMS sensor along with the analog circuitry and antenna is detailed. Techniques for packaging the device in order to meet the standards for safe operation are then presented. The report has dedicated chapters on review of the existing sensors, Inductive link design, CMOS control and Power conditioning circuit, Sensor Integration and Packaging. The principles, methods, systems and circuits described in this thesis are applicable to other implantable wireless systems which have stringent requirements on power and space.
Electronica Devices and Interface Strategies for Nanotechnology
(2007-04-12) Di Spigna, Neil Halen; Dr. Veena Misra, Committee Member; Dr. Paul Franzon, Committee Chair; Dr. John Muth, Committee Member; Dr. Gregory Parsons, Committee Member
Evaporation of ultra-thin layers of refractory metals onto glass substrates represents a relatively simple method of fabricating discontinuous metal films. The utility of these films in nanotechnology is based on the ability to control their morphology. In this thesis, control of discontinuous palladium films is demonstrated as the morphology is tailored for various applications. First, the films are successfully engineered to provide molecular scaffolding in the NanoCell. A dependency of the film morphology on the pattern density is observed which potentially could be exploited to provide wafer-scale morphology tuning with only a single evaporation. Next, electrical characterization of gold nanocrystal capacitors showed significant increases in the flat band voltage shift as the gold particle density increased. The density scaling of gold and palladium films was investigated revealing a linear dependence of gold on decreasing evaporation thickness and an exponential dependence for palladium. A palladium particle density of 1.03 x 10¹² particles cm⁻² was achieved, exceeding the theoretical target density for non-volatile memory applications. A novel technique to further increase this particle density is demonstrated. Another application for discontinuous metal films is for stochastic interface strategies. Interfacing the nanoworld with the microworld represents a critical challenge to fully integrated nanosystems. Unfortunately, not all applications can tolerate random or incomplete connectivity that can result from stochastic solutions. Therefore, a novel structure is presented that permits complete and deterministic cross-connect of orthogonal wiring arrays without the need for any critical translational alignment. Deterministically connecting 10nm wires directly to 3 µ wires would require a translational alignment to within only about 6 µ. It is shown that there is no restriction placed on the minimum nanowire pitch and that the design is independent of the technology used to fabricate the nanowires. The process is relatively simple and is presented from a fabrication perspective, critically evaluating the effect of potential processing errors on the design. A proof-of-concept structure is fabricated and analyzed, demonstrating the feasibility of this design.
Functional Verification of an ALU Core applying the Constrained Random approach
(2003-06-04) Hamilton, Patrick; Dr.Eric Rotenberg, Committee Member; Dr.Rhett Davis, Committee Member; Dr. Paul Franzon, Committee Chair
ASIC complexity is increasing so rapidly that designer productivity is not coping with the growth. Verification presents about 60-70% of the total design effort and only advances in verification methodology can improve the time to market considerably. Directed tests and 'golden' reference files will soon become the primitive tools of the modern test environment. Verification engineers are consequently looking towards new methodologies like Constrained-Random approach to reduce test bench development time, and speed-up the time it takes to achieve complete verification of their ASIC or SoC. Test bench automation tools for constrained-random stimulus generation and functional coverage create tests for corner cases that even engineers who designed the system may not anticipate and hence find bugs early in the development cycle. This thesis describes the study and implementation of the Constrained-Random concept in the Functional verification of a 32-bit ALU core using Specman.
Hardware Implementation of a Low Power Speech Recognition System
(2008-04-19) Pazhayaveetil, Ullas Chandra Sekhar; Dr. Paul Franzon, Committee Chair; Dr. Min Kang, Committee Member; Dr. Suleyman Sair, Committee Member; Dr. Rhett Davis, Committee Member
Inductively Coupled Interconnect for Chip to Chip Communication over Transmission Line
(2009-05-20) Shah, Chintan Hemendra; Dr. Paul Franzon, Committee Chair; Dr. Kevin Gard, Committee Member; Dr. Michael Steer, Committee Member
As data frequency increases beyond several Gbps range, low power chip to chip communication becomes more critical. The concept researched in this thesis is inductively coupled interconnect (LCI) over short length transmission line. The data will be transmitted across a 10 cm differential microstrip line on FR-4 material with a transformer on each side of the line. The transmitter and receiver circuits are designed in TSMC 0.18ÃŽÂ¼m process technology and can operate at 2.5 Gbps. The power consumption of the design is 5.53 mW at 2.5 Gbps which yields around 2.21 mW.Gb-1.s-1. This design can achieve BER of less than 10-12. The inductive coupling will reduce DC power because the low frequency DC component of the signal will be blocked by coupling inductors. The power consumed by this design is lower than most of the conventional I/Os that use physical contact interconnects. An H-bridge current steering driver is used at the transmitter and a differential amplifier and Sense-amp Flip flop is used at the receiver.
Memory Design for FFT Processor in 3DIC Technology
(2009-03-18) Gonsalves, Kiran; Dr. William Rhett Davis, Committee Member; Dr. Paul Franzon, Committee Chair; Dr. Eric Rotenberg, Committee Member
Computation of Fast Fourier Transform (FFT) of a sequence is an integral part for the Synthetic Aperture Radar (SAR). For FFT computations, there are a lot of data modification operations (multiplication and addition) involved. Typically, a memory (either on-chip or off-chip) would store the input data packet and output data would also be written to the same location. This memory would also be used as a scratch pad for storing intermediate results. As the required resolution of the image increases, the size of the input data increases. Hence, the number of computations in the butterfly structure of the FFT increases and this results in numerous data transactions between the memory and the computation units. Each data access can be expensive in terms of power dissipation and access time. The power dissipation is proportional to the size of the memory and the access time is dependent on the electrical proximity of the memory to the processing unit. Three Dimensional Integrated Circuits (3D IC) enable the tight integration of this memory with the logic that operates on the memory. Apart from form-factor improvement, 3D IC technology's main advantage is that it significantly enhances interconnect resources. Davis et al. in mention that in the best case, if the inter-tier vias are ignored, the average wire length can be expected to drop by number of tiers raised to the power of 2. This structure is advantageous as it reduces the access time and enables quicker computation of FFT when compared to its two dimensional counterpart. Alternatively, when run at the same speed, the 3D version can be said to dissipate lower power than the 2D version, owing to smaller interconnect parasitics. The electrical proximity of the memory enables more interconnections (wider buses) and as a result, many number of small memories can be interfaced to the processing elements. This would not be possible in the conventional off-chip structure as the number of interconnect pins would be a limiting factor due to limitations on pin-outs and Printed Circuit Board (PCB) routing. This thesis supports the demonstration of memory on logic in a 3D IC environment by creating a full custom memory. The two types of memories designed for the application are Static Random Access Memory (SRAM) (for storing input, intermediate and output data) and Read Only Memory (ROM) (for storing twiddle factors for FFT computation). For the application a dual ported SRAM cell is sufficient with one port for read and another port for write purposes. The FFT algorithm used ensures that any location in the memory is never read from and written to at the same time and this eliminates the necessity for a design that protects against simultaneous read/write. The ROM is required to store elements that do not change during the calculation of the FFT, i.e. the twiddle factors. In this project, a 32 x 64 SRAM including multiplexers and 3D TSVs is designed. This can be readily integrated into a 3DIC flow. The area for the SRAM is 0.155 square mm, giving an area of 75.68 square microns per bit. The access time for the SRAM is 1.7ns. The energy for read access is 408.79 fJ/bit. The energy for write access is 90.78 fJ/bit. A 129 x 52 ROM is designed with 3D TSVs. This can be integrated into a 3DIC flow. The area for ROM is 0.032922 square mm, giving an area of 4.72 square microns per bit. The access time for the ROM is 1ns. The energy per access is 165 pJ/bit.
Optical Network Processor Design For Just-In-Time Signaling Protocol Message Engine Design
(2002-11-18) Guled, Mohamed; Dr. Paul Franzon, Committee Chair
The purpose of this research has been the development of signaling protocol and associated architecture for Wave Division Multiplexing burst-switching network. The basic premise of this architecture is simple – data, aggregated in bursts can be transferred from one end point to the other by setting up light path ahead of the arrival of the data. Optical Burst switched network is viewed as one pioneering effort to bring the most bandwidth available from the emerging dWDM technologies to end applications with minimum overhead and latency.
A Scalable Architecture For Hardware Acceleration of Large Sparse Matrix Calculations
(2007-08-01) Hamlett, Matthew Issiah; Dr. Paul Franzon, Committee Chair; Dr. Gianluca Lazzi, Committee Member; Dr. Michael Steer, Committee Member
The task of implementing the Jacobi method has been looked at from several research works over the years. The Jacobi method is considered the most ideal Iterative method for implementation on FPGAs because of its inherent parallelism and lack of data dependencies. In this work, we look specifically at solving very large matrix equations in the form of Ax = b. Here A is a sparse matrix with dimensions of 1 million x 1 million with 6 entries per row. X is the vector we are solving for, and b is a known vector. All data is in 64-bit IEEE-754 floating point format. Previous work in this area has implemented the Jacobi method using only on chip memory accesses, greatly limiting the size of the matricies that can be solved. By using external memory, we present a design that is practical and can be used to accelerate various engineering and scientific problems today. In this design, we also implement the resources necessary for Multiple FPGAs to be used in a distributive manner so as to tackle larger problems. Our design gives a peak floating point performance of 1.8 GFLOPS and a sustained floating point performance of 1.18 GFLOPS. This is a speed up factor of around 2.95 when compared to the sustained performance that is typically seen on today's general purpose computers with this type of problem. To obtain this high peak floating point performance, we present in this paper a group of memory interfaces that are capable of supplying a total data rate of 20 Gb/sec sustained.