Browsing by Author "Dr. Rhett Davis, Committee Member"

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Adding Scalability to IBIS by Using AMS Languages
(2006-05-04) Fernando, Paul; Dr. Paul Franzon, Committee Chair; Dr. Kevin Gard, Committee Member; Dr. Rhett Davis, Committee Member
From 1993 to about 1998, IBIS remained THE digital IO buffer model format. But as the operating frequencies & complexity of I/O buffers increased, IBIS has been left behind in favor of SPICE models, since IBIS is inaccurate or unable to model these advanced buffers. This trend brings the industry back toward a single EDA vendor solution, which is what IBIS was designed to prevent. In an effort to relinquish these shortcomings, multi-lingual model extensions were added to IBIS Version 4.1. Specifically: Berkeley-SPICE, VHDL-AMS and Verilog-AMS files. These extensions in IBIS 4.1 give IBIS practically unlimited behavioral and structural modeling capabilities as well as more accuracy. The problem is that the AMS languages have been slow in making their way into SI tools and the SI community; mainly due to the associated learning curve, since AMS is relatively new to the SI world. The solution was to build an AMS library of tool independent basic elements ('element library') and a separate 'template library' which would contain the models of complex buffers (Pre-emphasis, LVDS, DDR2 etc). The templates would be created by instancing elements from the 'element library'. An IBIS to AMS converter would convert conventional IBIS files into AMS format and provide the data for the template. The IBIS macro-modeling committee was created in July 2005 with these main goals in mind. This thesis deals with the new AMS macro-modeling methodology put forth by the IBIS macro-modeling committee and the contributions I made to it as its only student member. My specific contribution was the IBIS to AMS (ibis2ams) converter tool. The thesis also presents the updates I made to the IBIS plotting utility (s2iplt) and the spice to IBIS toolkit (s2ibis). All tools are publicly available on the NCSU ERL website.
FPGA Implementation of a Low Power Doppler Invariant BFSK Receiver
(2003-09-03) Arkesh, Vikram; Dr. J Keith Townsend, Committee Member; Dr. Paul D. Franzon, Committee Chair; Dr. Rhett Davis, Committee Member
A non coherent frequency shift keying (FSK) receiver architecture is designed potentially for low power applications. The receiver incorporates a 16 point Fast Fourier Transform (FFT) for symbol detection and can withstand large Doppler shifts. Almost all the design units of the receiver are digital designs for better power efficiency and reliability. The receiver functions on one bit data processing and supports data rates of 10kbps, 1kbps and 100bps. Co-ordinate rotation (CORDIC) algorithm is used for complex multiplications while computing FFT, evading the use of power hungry multipliers. The design and simulation of the receiver is carried out in MATLAB/SIMULINK. The MATLAB model is translated to a XILINX FPGA hardware model using system generation features of the XILINX development system. The hardware model is synthesized to a virtex-2 XILINX FPGA and various performance parameters are extracted. A control system for symbol and timing detection is designed and modeled in VHDL, synthesized to XILINX hardware and interfaced to the receiver.
Hardware Implementation of a Low Power Speech Recognition System
(2008-04-19) Pazhayaveetil, Ullas Chandra Sekhar; Dr. Paul Franzon, Committee Chair; Dr. Min Kang, Committee Member; Dr. Suleyman Sair, Committee Member; Dr. Rhett Davis, Committee Member
High-Speed Transceiver Design in CMOS using Multi-level (4-PAM) Signaling
(2003-04-22) Joseph, Balu; Dr. Gianluca Lazzi, Committee Member; Dr. Wentai Liu, Committee Chair; Dr. Rhett Davis, Committee Member
The design of a 4 Gbps serial link transceiver in 0.35μm CMOS process is presented. The major factors limiting the performance of high-speed links are transmission channel bandwidth, timing uncertainty and on-chip frequency limitations. The design uses a combination of multi-level signaling (4-PAM) and transmit pre-emphasis to overcome the channel low-pass characteristics. High on-chip frequency signals are avoided by multiplexing and de-multiplexing the data directly at the pads. Timing recovery is done through over-sampling the data using multi-phase clocks generated from a low-jitter PLL. The design achieves a 4 Gbps data transmission rate, with a transmit data jitter of 53.2 ps (p-p), while consuming 879.4 mW of power from a 3.3 V supply.
Scheduling to Consolidate Idle Periods for Energy-Efficiency in Multicore Systems.
(2009-09-29) Pal, Poulomi; Dr. Gregory T. Byrd, Committee Chair; Dr. Eric Rotenberg, Committee Member; Dr. Rhett Davis, Committee Member
PAL, POULOMI. Scheduling to Consolidate Idle Periods for Energy Efficiency in Multicore Systems. (Under the direction of Dr. Gregory T. Byrd.) Power-efficiency and energy savings are the major drivers in the CPU design space. Design at all levels needs to be energy-aware in order to be considered seriously. With the emergence of mobile devices as a large market, energy efficiency has become of prime importance, as the emphasis now lies on making the battery last longer. Most modern cellphones are required to do much more than making and receiving calls. With 4G approaching quickly, the cellphone is required to be almost as good as any general purpose computer with respect to application complexities. This gives rise to the need for adaptive systems that can handle applications with high performance, and conserve energy as well. The research presented here provides a scheduling scheme which aims to consolidate CPU idle times, and to introduce some amount of inertia and determinism in the system, so as to provide the opportunity to switch CPUs into low-power modes for conservation of energy. The baseline used here is the Linux kernel-2.6.28, which implements distributed control for load balancing for different CPUs. Changes are made to this kernel, and CPU activity is used as the metric for comparison. It is found that the CPUs that are numbered higher get much longer idle periods, which can be used for switching to energy-efficiency mode, while still maintaining comparable performance.
Transient Electrothermal Modeling of Digital and Radio Frequency Circuits.
(2006-08-24) Luniya, Sonali R.; Dr. Michael B. Steer, Committee Chair; Dr. Kevin G. Gard, Committee Member; Dr. Paul D. Franzon, Committee Member; Dr. Rhett Davis, Committee Member
Simulator technology for the high dynamic range, electrothermal modeling of electronic circuits is developed and applied to digital, radio frequency (RF) and microwave circuits. High-dynamic range is achieved using a combination of device models based on state-variables and utilizing automatic differentiation, precise error determination, and time step control. State-variables enable simpler and faster development of models less prone to implementation error. Automatic differentiation yields error free evaluation of the derivatives of circuit quantities with respect to each other and so removes any uncertainty in establishing the precise circuit condition. In transient analysis precise error determination and time step control is achieved by comparing two nonlinear solutions at each time point. A two-tone test of an X-band GaAs MESFET MMIC (Gallium Arsenide, Metal Semiconductor Field Effect Transistor Monolithic Microwave Integrated Circuit) was used to investigate and validate dynamic range. In the determination of the third-order intermodulation product in a two tone test a dynamic range of 165 dB was demonstrated. This high dynamic range was achieved through precise evaluation of the derivatives, accurate time step control and the circuit state, which is important in long electrothermal transient simulations. This minimization of accumulated numerical error is especially important in long electrothermal transient simulations. The 3D compact thermal models of the X-band MMIC LNA developed were verified with thermal images of the MMIC LNA taken with an infra red camera. The thermal models predict the temperature rise on various spots of the MMIC with less than 5% error. To perform an coupled electrothermal simulation at RF frequencies, a linear RC network based thermal macromodel of the MMIC was developed. The high dynamic range capability helped detect the small changes in the output voltage of the MMIC, at elevated temperatures. This thermal macromodel was applied to electrothermal simulations of an 3D thermal test chip designed with a 0.18 um Fully Depleted Silicon on Insulator (FDSOI) MOSFET (Metal Oxide Semiconductor Field Effect Transistor) technology. An experimentally validated state-variable based electrothermal model of a 0.18 um FDSOI MOSFET is implemented.