Browsing by Author "Dr. Suleyman Sair, Committee Member"

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Cache Line Boundary Allocation for Garbage Collected Systems
(2007-08-22) Wagle, Prasad Ajit; Dr. Suleyman Sair, Committee Member; Dr. Yan Solihin, Committee Member; Dr. Edward F Gehringer, Committee Chair
Characterization of Context Switch Effects on L2 Cache
(2007-04-16) Eker, Abdulaziz; Dr. Yan Solihin, Committee Chair; Dr. Suleyman Sair, Committee Member; Dr. Ed Gehringer, Committee Member
Multitasking is common in most systems. In order to use the processor resources efficiently, a multitasking system schedules processes to run for certain intervals by switching (saving and restoring) their contexts. However, since processes bring their own data to the cache when they are running, context switching causes each process to suffer from more misses. Behavior of L2 cache misses due to context switches with different cache configurations, working-set sizes, and process priorities is not well-understood. Analysis of this behavior will give insights about the reasons and ways to mitigate these misses. The first contribution of this paper is the characterization of the context switch effect on L2 cache relating to the process priorities. The paper also characterizes the context switch effect with various cache configurations, including the size and associativity of the cache. Finally, it defines two types of misses that occur due to context switches.Replacement context switch misses occur when a process' working set is replaced by an interfering process. Reorder context switch misses occur due to reordering of lines by an interfering process, i.e. moving lines from more recently used to less recently used position. Based on the characterization results, we found that the number of context switch misses increases with lower priorities. On average, a process with the lowest priority suffers 15.4 times more L2 cache misses due to the context switch effect than the case there is no time-sharing, while the process with the highest priority suffers only 1.2 times more misses. We also observed that the impact of context switch is affected more by the priority of the process itself, rather than the priority of the interfering process. We also found that increase in associativity increases reorder context switch misses. Finally, the highest number of context switch misses occur when the size of a process' working set is close to the cache size.
Design and Analysis of Lock-free Data Structures
(2007-07-31) Sarkar, Abhik; Dr. Yan Solihin, Committee Chair; Dr. Suleyman Sair, Committee Member; Dr. Ed Gehringer, Committee Member
The advent of multi-processor systems has motivated programmers to develop multi-threaded and multi-process applications on shared memory data structures. In these applications, multiple processes read and update shared data structure concurrently, which may lead to race conditions resulting in incoherent memory. To ensure exclusivity of access to this shared memory, programmers have been using locks. Lock-based concurrency is a pessimistic approach that assumes conflicts among concurrent processes to occur frequently.However, if few conflicts occur, lock-based concurrency unnecessarily reduce concurrency. One solution to improve concurrency, is to allow non-conflicting processes to execute in parallel. This can be gained by using fine locks, but programming with them is complex and error-prone. Consequently, researchers have devised an optimistic concurrency mechanism known as lock-free algorithms. Various lock-free libraries have been developed that are either data structure specific or universal constructs. However, these lock-free libraries have been restricted to simple data structures that do not meet the requirements of a real-world application. This work focuses on implementing a lock-free data structure suitable for a real-world application. The suitability of various implementations is analyzed. Design choices are made based upon the requirements and the suitability of lock-free implementations to the specific application considered. Finally, the performance of the lock-free implementation versus lock-based implementation are compared. Along with it, certain insights related to reduced complexity of the implementation and atomicity of lock-free implementation that make it robust are discussed.
Hardware Implementation of a Low Power Speech Recognition System
(2008-04-19) Pazhayaveetil, Ullas Chandra Sekhar; Dr. Paul Franzon, Committee Chair; Dr. Min Kang, Committee Member; Dr. Suleyman Sair, Committee Member; Dr. Rhett Davis, Committee Member
Improving Transient Fault Tolerance of Slipstream Processors
(2005-12-12) Parthasarathy, Sailashri; Dr. Eric Rotenberg, Committee Chair; Dr. Suleyman Sair, Committee Member; Dr. Jun Xu, Committee Member
A slipstream processor runs two copies of a program, one slightly ahead of the other, to achieve both higher single-program performance and transient fault tolerance. The leading copy of the program, or the Advanced Stream (A-stream), is accelerated by executing only a key subset of all instructions. The partial A-stream is speculative. Therefore, a second, complete copy of the program, called the Redundant Stream (R-stream), receives and checks all A-stream outcomes. The R-stream is also accelerated in this process. Together, the A-stream and R-stream finish faster than a single program copy would. The partial redundancy between the A-stream and R-stream enables detection and recovery from transient faults. A transient fault that affects a redundantly executed instruction is easily detected, because its two instances will differ. However, a transient fault that affects a singly executed instruction (instruction removed from A-stream) is difficult to detect directly, because there is no redundant counterpart for comparison. Actually, a fault in a singly executed instruction is indirectly detectable via a redundantly executed consumer. However, such a fault is unrecoverable since the fault is attributed to the consumer. Recovery is initiated too late, from the consumer instead of the faulty producer. We propose a mechanism that conservatively attributes a detected fault, not to the redundantly executed instruction that detected it, but to its singly executed producer. Accordingly, recovery is initiated safely from the singly executed producer. Our approach works by forming a forward slice for each singly executed instruction, terminating in its direct/indirect redundantly executed consumers. Now, a consumer can mark its singly executed producer as faulty when its comparison mismatches. A singly executed branch does not have a forward slice and thus is not checkable by consumers. However, the branch was removed from the A-stream precisely because its branch prediction is highly confident, hence, very likely correct. This likely correct branch prediction is treated as a second execution for the corresponding singly executed branch, different from true execution but nearly as effective for detecting faults. In fact, the observation about confident branches extends to all redundantly executed instructions since the A-stream is predictive as a whole. All A-stream instructions are speculative, yet most likely correct in the fault-free case. This reveals an intriguing predictive checking paradigm. Experiments using the SPEC95 and SPEC2K benchmarks show that coverage improves from 81% for baseline slipstream to 99% with only a small decrease in speedup. To obtain the same performance as baseline slipstream, we propose a relaxed checking model, which still achieves a much higher coverage of 95%.
Page Pinning Improves Performance of Generational Garbage Collection
(2006-05-04) Sawyer, Richard Kevin; Dr. Edward F. Gehringer, Committee Chair; Dr. Gregory T. Byrd, Committee Member; Dr. Suleyman Sair, Committee Member
Garbage collection became widely used with the growing popularity of the Java programming language. For garbage-collected programs, memory latency is an important performance factor. Thus, a reduction in the cache miss rate will boost performance. In most programs, the majority of references are to newly allocated objects (the nursery). This work evaluates a page-mapping strategy that pins the nursery in a portion of the L2 cache. Pinning maps nursery pages in a way that prevents conflict misses for them, but increases the number of conflict misses for other objects. Cache performance is measured by the miss-rate improvement and speedup obtained by pinning on the SPECjvm98 and the DaCapo benchmarks. Pinning is shown to produce a lower global miss rate than competing virtual-memory mapping strategies, such as page coloring and bin hopping. This improvement in miss rate shortens overall execution time for practically every benchmark and every configuration. Pinning greatly reduces average pause time and variability of pause times for nursery collections.
PMPT - Performance Monitoring PEBS Tool
(2006-08-11) Beu, Jesse Garrett; Dr. Suleyman Sair, Committee Member; Dr. Gregory T. Byrd, Committee Member; Dr. Thomas M. Conte, Committee Chair
For many applications a common source of performance degradation is excessive processor stalling from high memory latencies or poor data placement. Performance degradations from program and memory hierarchy interactions are often difficult for programmers and compilers to correct due to a lack of run-time information or limited knowledge about the underlying problem. By leveraging the Pentium 4 processor's performance monitoring hardware, specific run-time information can be provided, allowing code modifications to reduce or even eliminate problematic code, resulting in reduced execution times. Furthermore, many tools currently available to aid programmers are program counter centric. These tools point out which area of the code produce slowdowns, but they do not directly show where the problem data structures are. This is a common problem in programs that dynamically allocate memory. By creating a "malloc-centric" tool, we can develop an interesting perspective of the memory behavior of the system, providing better insight into the sources of performance problems.
Preliminary Study of Trace-Cache-Based Control Independence Architecture.
(2006-05-23) Al-Otoom, Muawya Mohamed; Dr. Eric Rotenberg, Committee Chair; Dr. Suleyman Sair, Committee Member; Dr. W. Rhett Davis, Committee Member
Conventional superscalar processors recover from a mispredicted branch by squashing all instructions after the branch. While simple, this approach needlessly re-executes many future control-independent (CI) instructions after the branch's reconvergent point. Selective recovery is possible, but is complicated by the fact that some control-independent instructions must be singled out for re-execution, namely those that depend on data influenced by the mispredicted branch. That is, control-independent data-dependent (CIDD) instructions must be singled out for re-execution, thus avoiding needless re-execution of control-independent data-independent (CIDI) instructions. To contrast different recovery models, we abstract the recovery process as constructing a "recovery sub-program" for repairing partially incorrect future state. In this conceptual framework, selective recovery constructs a shorter recovery sub-program than full recovery. In current selective recovery microarchitectures, the recovery sub-program is constructed on-the-fly after detecting a mispredicted branch, by sequencing through all CI instructions and singling out only the CIDD instructions among them. Not only is this discriminating approach complex, but the same recovery sub-program is repeatedly constructed every time this branch is mispredicted. We propose constructing the recovery sub-program for each branch once and caching it for future use. In particular, traces of CIDD instructions are pre-constructed and stored in a recovery trace cache. When a misprediction is detected, first, the branch's correct control-dependent instructions are fetched from the conventional instruction cache as usual. Then, at the reconvergent point, fetching simply switches from the instruction cache to the recovery trace cache. The appropriate recovery trace is fetched from the recovery trace cache at this time. In this way, fetching only the CIDD instructions is as simple as fetching all CI instructions from a conventional instruction cache. No explicit singling-out process is needed as this was done a priori, on the fill-side of the trace cache. Therefore, the recovery trace cache is efficient on multiple levels, combining the simplicity of full recovery with the performance of selective recovery. This thesis explains the proposed trace-cache-based control independence architecture, at a high level. Preliminary studies are also presented, to project the potential of exploiting control independence as well as the effectiveness of a trace-cache-based approach in particular. The results include (i) breakdowns of retired dynamic instructions into different categories, based on their control and data dependences with respect to prior mispredicted branches, (ii) contributions of individual recovery traces to total CIDI instruction savings, and (iii) hit ratios of finite recovery trace caches.
A Simulator for Microcontroller-based Underwater Ultrasonic Communications
(2006-08-04) Govilkar, Samir Rajshekhar; Dr. Mihail L. Sichitiu, Committee Member; Dr. Alexander G. Dean, Committee Chair; Dr. Suleyman Sair, Committee Member
The aim of this thesis is to aid in the development of the RAPTEX project. The RAPTEX project deals with designing efficient communication protocols for underwater telemetry and sensor networks. Underwater telemetry is used to track crabs, initially in shallow water and later in marine environments. Ultrasonic waves are used for such underwater telemetry. The ultrasonic waves are affected by various phenomena as they pass through water. These phenomena include attenuation, multi-path fading, noise, etc. A small microcontroller based transmitter will be placed on the back of the crab allowing the telemetry data to be transmitted. The microcontroller will directly drive an ultrasonic transducer through a Digital to Analog Converter to output a modulated carrier wave. It is necessary to simulate the communication between the microcontroller based transmitter and the receiver before testing this system in the real-world environment. The purpose of the simulation is two-fold. It helps to validate the design and it also helps in verifying the end-to-end communication of the system. This becomes important as more and more higher layer protocols are added to the RAPTEX project. Since the simulation environment has control over all the parts of the communication system; viz. the transmitter (based on the AVR microcontroller), the channel and the receiver, it is possible to inspect the flow of data at any point by adding suitable taps.
Transparent Control Independence (TCI)
(2007-08-14) Al-Zawawi, Ahmed Sami; Dr. Suleyman Sair, Committee Member; Dr. Warren J. Jasper, Committee Member; Dr. Eric Rotenberg, Committee Chair; Dr. Thomas M. Conte, Committee Member