Browsing by Author "Dr. William Rhett Davis, Committee Chair"

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    Architectures and Design Methodology for Energy Efficient MIMO Decoders
    (2009-02-23) Jenkal, Ravi Somnath; Dr. Xun Liu, Committee Member; Dr. Ilse Ipsen, Committee Member; Dr. Winser Alexander, Committee Member; Dr. Paul Franzon, Committee Member; Dr. William Rhett Davis, Committee Chair
    This work focuses on the design and implementation aspects of Multi-Input Multi-Output (MIMO) decoders for multi-antenna communications. These decoders are used to determine, either optimally or sub-optimally, the bits encoded and transmitted over a wireless channel with more than one antenna. Present standards, such as 802.11n and 4G, call for systems with more than the present two antennas. Additionally, the need for future considerations of mobility along with lowered current limits of smaller technology nodes, calls for greater power awareness in the design of MIMO decoders. The presence of multiple antennas brings with them a) an exponentially large space for a min-cost search for the solution and b) non-trivial VLSI requirements to deal with additional dimensions of the wireless channel. Additionally, the conditions under which a MIMO decoder is used would change in terms of the Signal to Noise Ratio (SNR) values. This requires considerations in the multiple axes for a decoder implementation: Power, Delay, throughput and algorithmic performance. Of the many options available, Sphere Decoding (SD) has become a popular implementation of MIMO detection due to its improved performance at lower hardware complexity in comparison with Maximum Likelihood methods for optimal algorithmic performance. ASIC implementations have proven the feasibility of this method but fail to effectively address the issue of energy efficiency (b/s/mW). In this work, we investigate the architectural and design space of multi-antenna decoders. We show that systems that allow for tradeoffs along multiple axes are more likely to achieve energy optimality due to a changing usage environment. Multi-antenna systems are unique because they can exploit parallelism which could aid in amortizing the constraints on design. We design and implement improved architectures that exploit a combination of a deeper pipelines and simple single-port read and write memories to increase the energy efficiency (bits/sec/mW) of the decoding process. We also implement architectural modifications that increase the throughput of algorithmically optimal decoders. We use these improvements to make an argument for increased power consumption with the final aim of improving the energy efficiency of decoding. Additionally, we also provide insights into the design of architectures that can handle an increased constellation size and increased antenna numbers in a power efficient manner. In an effort to improve the throughput, we also provide a simple method of a block based algorithm using counters. VLSI implementation of all the architectures proposed provides the final measure of complexity in terms of power, area and throughput. The implementation of the proposed architectures in a 1.2V 90nm 8-metal IBM process demonstrates the effectiveness of the various methods proposed in reducing complexity and increasing energy efficiency.
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    Network-on-Chip Optimization: as shown through a novel LDPC Decoder Design
    (2010-04-02) Mineo, Christopher Alexander; Dr. Gregory T. Byrd, Committee Member; Dr. Paul D. Franzon, Committee Member; Dr. Donald L. Bitzer, Committee Member; Dr. William Rhett Davis, Committee Chair
    In this work we describe the network-on-chip (NoC) simulator, which fills the gap between architectural level and circuit level NoC simulation. The core is a fast, high level transaction-based NoC simulator, which accesses carefully compiled power, timing, and area models for basic NoC components built from detailed circuit simulation. It makes use of the architectural evaluator, which performs a detailed global interconnect analysis within the framework of industry-standard design tools. Using low density parity check decoding (LDPC) as a test vehicle, the NoC simulator is used in an NoC design study, and shows a method by which on-chip networks can be optimized. The foundation for architectural and transaction based modeling is set by a demonstration of the functional 3D NoC Test Chip, a 3-ary 3-cube on-chip interconnection network implemented in a 3-tier three dimensional integrated circuit (3DIC) technology. The chip, being among the first and only functional synthesized academic 3DIC's, not only demonstrates the feasibility of inter-tier signaling in a 3DIC, but has enabled power measurements that bring credibility to our power modeling methodology. We discuss a characterization methodology for parameterized NoC router components, so that we can quickly and easily estimate the power, performance, and area overhead for a wide range of NoC systems. While the completed models are provided so that they may be used for architectural evaluation independent from the remainder of our simulation framework, we describe the architecture of the NoC simulator. The simulator is used to study various LDPC and NoC parameters to help with high level design decision making. The results make a compelling case for the 2D and 3D torus networks and very shallow network memory buffers. We also introduce the concept and show the importance of processing element throttle. Using the simulator, a pareto optimal set of NoC configurations for our application is produced.