Browsing by Author "Dr. Winser E. Alexander, Committee Chair"

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Design and Performance Characterization of a Test System for Microprocessor Hot Spot Cooling using Thin-film Superlattice Thermoelectrics
(2004-01-25) Cancheevaram, Jai Kumaran Kuppuswamy; Dr. Winser E. Alexander, Committee Chair; Dr. John F. Muth, Committee Member; Dr. Ronald O. Scattergood, Committee Member
The constant need for higher performance, increased levels of functional integration, as well as die size optimization has led to preferential clustering of higher power units on microprocessors. This causes higher heat flux concentrations in certain areas of the die and lower heat fluxes in certain other regions, which manifest themselves as large temperature gradients on the die surface. These local power densities are commonly referred to as 'hot spots'. The thermal cooling solution provided must effectively ensure that junction/die temperatures on the processor does not exceed the rated 90-110 °C range, to guarantee device performance and reliability. The focus of this work is to present Thin-film Superlattice Thermoelectrics [TFST] as an excellent solution for microprocessor die Hot spot cooling. TFSTs have measured Figure of Merit [ZT] values of ~2.4 at 300K for p-type superlattices, with potential to pump heat flux of up to 700Wcm-2. Furthermore, these devices have fast response times, which makes them achieve steady state cooling in 15μs. This is vital in preventing thermal runaway and subsequent failure of microprocessors during rapid load transients. The primary contribution of this thesis is a test setup and experimental procedure, for characterization of an integrated TFST-processor system. First I identified and isolated potential hot spots on the processor using infrared (IR) images of the die during operation. The IR images were conclusive in determining the area of these hot spots and their magnitudes in terms of maximum temperatures reached. Next I calculated the power dissipated by the processor on the basis of the heat absorbed by the cooling system. This involved building a calorimetric system, which cools the processor by circulating water. The system was calibrated with a known load and found to measure within +3 watts of the actual power dissipated, for a processor thermal design power of 30 watts. Using this system, calculations of heat dissipated by the processor under both normal clocking and over clocking cases are presented. The final step in integrating the TFST with the processor involved mounting the TFST module onto the processor hot spot and ensuring safe operation. The TFST module itself was powered by a custom-modified Howland Current source circuit, which regulated the amount of cooling. Further contributions of this thesis include evaluating the efficiency of the TFST and the resulting impact on microprocessor performance and reliability. The temperature at interface of the TFST module and hot spot was monitored during several stages of CPU operation. Thermal transients at the hot spots is presented in the results show that active heat spreading using TFST significantly reduces the thermal cooling budget and alleviates constraints on the cooling solution. In future, with more efficient TFST modules with higher ZT values, these hot spots may be completely eliminated.
An Efficient FPGA Implementation of the Discrete Wavelet Transform
(2008-09-25) Dalal, Ishita; Dr. W. Rhett Davis, Committee Member; Dr. William W. Edmonson, Committee Member; Dr. Winser E. Alexander, Committee Chair
Flexible ASIC Design using the Block Data Flow Paradigm (BDFP)
(2002-05-27) Deng, An-Te; Dr. Winser E. Alexander, Committee Chair; Dr. Clay S. Gloster, Committee Member; Dr. Paul D. Franzon, Committee Member; DR. Zhilin Li, Committee Member
An Application Specific Integrated Circuit (ASIC) outperforms most processors; however, it is limited to one algorithm. Instruction Level Parallelism (ILP) processors, which include mixed type processors such as the Digital Signal Processor (DSP), the Very Long Instruction Word (VLIW) Processor, the Reduced Instruction Set Computer (RISC), and the Complex Instruction Set Computer (CISC), are popular due to their flexibility and programmability. Thus, they can be used for many different applications. However, their cost-performance can not meet the needs of many real world applications. In this research, we mapped three different algorithms, the one-dimensional Finite Impulse Response (1D-FIR), the two-dimensional Finite Impulse Response (2D-FIR), and the two-dimensional Infinite Impulse Response (2D-IIR) filter into the same flexible hardware architecture using the Block Data Flow Paradigm (BDFP). The idea of a Flexible Application Specific Integrated Circuit (FASIC) is to design a mixed architecture using an ASIC for the fixed part of the system while using a Field Programmable Gate Array (FPGA) for the part of the system that requires a change of parameters for different algorithms. The Block Data Flow Parallel Architecture (BDPA) design, which has near super computer performance for media processing, is meant to form part of the FASIC library (Intellectual Property, IP) and is to be integrated with a general purpose host computer or mixed processor computer as an accelerator. The FASIC, designed in this research, not only can accommodate different algorithms but also can flexibly change its configuration to obtain different cost-performance and frequency response outputs according to each system specification. We used the block data overlap-save algorithm for implementing the FIR filter system. This allows linear speedup performance if proper data input/output (I/O) and block size are given. We used the state space concept to implement the 2D-IIR filter system, which also has the characteristic of linear speedup to a saturation point. In order to solve the data flow bottleneck problem which exists in most multiprocessor systems, we have designed a hierarchical data flow control architecture, an input data distributor, and a data source regulator. These designs are flexible and asynchronously controllable so that they can easily accommodate different algorithms. We used a one dimensional array architecture to reduce wafer area, pin connections, and power consumption (compared to a 2D array architecture). We used a four processor module array in the 2D-FIR filter system, which was designed on a multiprocessor system using a clock with two different frequencies. This system has throughput performance of 7.975 samples per processor clock cycle and the processor utilization is 78.53%.
Implementation of the Two Dimensional Integer Wavelet Transform for Transmission of Images
(2004-11-03) Joseph, Smitha; Dr. W. Rhett davis, Committee Member; Dr. Wesley E. Snyder, Committee Member; Dr. Winser E. Alexander, Committee Chair
Applications like telemedicine require the diagnostic information in the form of very large images to be transferred using existing networks. These applications use region of interest coding in medical images to reduce the cost while meeting the diagnostic quality requirements. The Integer Wavelet Transform is the major component in the JPEG 2000 based dynamic region of interest coding scheme. The wavelet transform helps to concentrate the signal energy to fewer coefficients to increase the degree of compression when the data is encoded. The wavelet transform is a computationally intensive component and the computations can be accelerated for real time applications like telemedicine by implementing the algorithm in hardware. Since the reconstruction of the medical images should be done with little or no loss to maintain diagnostic accuracy, we are interested in a lossless implementation of the wavelet transform. This thesis investigated the approaches to be used in the hardware implementation of the two dimensional integer wavelet lifting algorithm using the bi-orthogonal (9,7) filter. It proposes an implementation of a hardware model that meets the stringent quality requirements and is suitable for transmission of images for applications like telemedicine. The major design issues considered in the design of the 2D-integer wavelet transform architecture were the round off errors due to the use of fixed point arithemetic to perform the computations, the waiting time between the row and column processing, the memory access time and the implementation of the non-causal lifting structure. The round off errors in fixed point computations were reduced through scaling, sign extension and rounding. The proposed hardware model has a high throughput rate because it does the row and column processing in a single pass which avoids the waiting time between the row and column processing. This is done with substantial savings in memory over the more traditional level based designs. An architecture based on the data dependency graph was developed that overcame the difficulty posed by the non-causal lifting structure. The results obtained from the test cases on 8 bit gray scale images show that this 2D hardware model yields very good performance. The hardware model reconstructed the test images without any error.
A Methodology for Hardware Design and Verification of Architectures for Channel Equalization
(2005-12-02) Patel, Virendra Rameshbhai; Dr. Winser E. Alexander, Committee Chair; Dr. Rhett W. Davis, Committee Member; Dr. Eric Rotenberg, Committee Member
Hardware implementing wireless applications in today's cellular systems has stringent requirements such as high speed, flexibility, and low power dissipation resulting in complex systems. These requirements have led to the development of systems on a single chip. Although this development promises a variety of design advantages, designers are facing new design difficulties and challenges while designing these complex systems. Some of the design difficulties and challenges presented by the traditional design flow, in designing these complex systems, are increase in the simulation time, increase in the verification effort required, increase in the time to market, difficulty in exploring the design space, and increase in the productivity gap. In this research work, we introduce a new design flow that starts at the system level. The design flow, called the system-level design flow, promises to reduce the difficulty in exploring the design space, to reduce the simulation times, to reduce the verification and debugging time, to allow the definition of both hardware and software components of a design, and to allow defining the system at a high level of abstraction. To validate our design flow and its advantages, we consider a subsystem for a Wireless Communication System called a 'Multiple Input Multiple Output' (MIMO) wireless communication system for analysis. We consider the designs of channel equalization architectures for the MIMO wireless communication system. We consider algorithms such as least mean square and iterative conjugate gradient algorithms for implementing channel equalization. We design the algorithms using SystemC and Verilog. We consider the use of SystemVerilog to interface SystemC to the Verilog environment.