Browsing by Author "Eric Rotenberg, Member"

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Analysis of Finite State Automata and Transducers Processing Acceleration on Disparate Hardware Technologies.
(2020-11-30) Nourian, Marziyeh; Michela Becchi, Chair; Eric Rotenberg, Member; Huiyang Zhou, Member; Rainer Mueller, Member
An Analysis of Subthreshold SRAM Bitcells for Operation in Low Power RF-only Technologies.
(2013-07-23) Schabel, Joshua Chris; Paul Franzon, Chair; Eric Rotenberg, Member; William Davis, Member
Analyzing and Accelerating Runtime Systems on Multicore Architecture
(2013-04-29) Tiwari, Devesh; Yan Solihin, Chair; James Tuck, Member; Xiaosong Ma, Member; Eric Rotenberg, Member
Architectural and Compiler Issues for Tolerating Latencies in Horizontal Architectures
(2001-09-04) Ozer, Emre; Thomas M. Conte, Chair; Edward W. Davis, Member; Wentai Liu, Member; Eric Rotenberg, Member
This dissertation presents a new architecture model named Weld for horizontal architectures such as VLIW and EPIC. Weld integrates speculative multithreading support into a VLIW/EPIC processor to hide run-time latency effects that cannot be determined by the compiler. Also, it proposes a hardware technique called operation welding that merges operations from different threads to utilize the hardware resources more efficiently. Hardware contexts such as program counters and the fetch units are duplicated to support multithreading. Also, a dual-thread Weld architecture is isolated and analyzed for cost/performance purposes within the general Weld architecture. The dual-thread Weld model supports one main thread and one speculative thread running simultaneously in a VLIW/EPIC processor with a register file and a fetch unit per thread. The cost/performance impact of the dual-thread Weld model, which includes analysis of migrating the disambiguation hardware to the compiler and the sensitivity analysis to the variation of branch misprediction and second-level cache miss penalties, is examined further.
A Bottom-Up SLP Vectorization Pass Starting from Associative Reduction Chains Implemented in LLVM
(2015-05-26) Mabe, David Michael; James Tuck, Chair; Eric Rotenberg, Member; Huiyang Zhou, Member
Compiler-Driven Value Speculation Scheduling
(2001-05-10) Fu, Chao-ying; Thomas M. Conte, Chair; Paul D. Franzon, Member; Wentai Liu, Member; Eric Rotenberg, Member
Modern microprocessors utilize several techniques for extracting instruction-level parallelism (ILP) to improve the performance. Current techniques employed in the microprocessor include register renaming to eliminate register anti- and output (false) dependences, branch prediction to overcome control dependences, and data disambiguation to resolve memory dependences. Techniques for value prediction and value speculation have been proposed to break register flow (true) dependences among operations, so that dependent operations can be speculatively executed without waiting for producer operations to finish. This thesis presents a new combined hardware and compiler synergy, value speculation scheduling (VSS), to exploit the predictability of operations to improve the performance of microprocessors. The VSS scheme can be applied to dynamically-scheduled machines and statically-scheduled machines. To improve the techniques for value speculation, a value speculation model is proposed as solving an optimal edge selection problem in a data dependence graph. Based on three properties observed from the optimal edge selection problem, an efficient algorithm is designed and serves as a new compilation phase of benefit analysis to know which dependences should be broken to obtain maximal benefits from value speculation. A pure software technique is also proposed, so that existing microprocessors can employ software-only value speculation scheduling (SVSS) without adding new value prediction hardware and modifying processor pipelines. Hardware-based value profiling is investigated to collect highly predictable operations at run-time for reducing the overhead of program profiling and eliminating the need of profile training inputs.
Cross-Layer Approaches for Architectural Vulnerability Estimation to Improve the Reliability of Superscalar Microprocessors
(2017-06-30) Wibowo, Bagus Prasetyo; James Tuck, Chair; Eric Rotenberg, Member; Gregory Byrd, Member; Daowen Zhang, Graduate School Representative; Xiaohui Gu, Member
Design of On-chip Bus of Heterogeneous 3DIC Micro-processors.
(2016-06-20) Zhang, Zhenqian; Paul Franzon, Chair; William Davis, Member; Eric Rotenberg, Member; Min Kang, Member
Dynamic Frequency and Voltage Scaling in Rivalrous Real-time Embedded Systems.
(2013-08-20) Parsons, Gregory Scott; Alexander Dean, Chair; Eric Rotenberg, Member; Vincent Freeh, Member; James Tuck, Member
Dynamic Optimization Infrastructure and Algorithms for IA-64
(2000-06-29) Hazelwood, Kim Michelle; Thomas M. Conte, Chair; Eric Rotenberg, Member; Injong Rhee, Member
Dynamic Optimization refers to any program optimization performed after the initial static compile time. While typically not designed as a replacement for static optimization, dynamic optimization is a complementary optimization opportunity that leverages a vast amount of information that is not available until runtime. Dynamic optimization opens the doors for machine and user-specific optimizations without the need for original source code. This thesis includes three contributions to the field of dynamic optimization. The first main goal is the survey of several current approaches to dynamic optimization, as well as its related topics of dynamic compilation, the postponement of some or all of compilation until runtime, and dynamic translation, the translation of an executable from one instruction-set architecture (ISA) to another. The second major goal of this thesis is the proposal of a new infrastructure for dynamic optimization in EPIC architectures. Several salient features of the EPIC ISA prove it to be not only a good candidate for dynamic optimization, but such optimizations are essential for scalability that is up to par with superscalar processors. By extending many of the existing approaches to dynamic optimization to allow for offline optimization, a new dynamic optimization system is proposed for EPIC architectures. For compatibility reasons, this new system is almost entirely a software-based solution, yet it utilizes the hardware-based profiling counters planned for future EPIC processors. Finally, the third contribution of this thesis is the introduction of several original optimization algorithms, which are specifically designed for implementation in a dynamic optimization infrastructure. Dynamic if-conversion is a lightweight runtime algorithm that converts control dependencies to data dependencies and vice versa at runtime, based on branch misprediction rates, that achieves a speedup of up to 17% for the SpecInt95 benchmarks. Several other algorithms, such as predicate profiling, predicate promotion and false predicate path collapse are designed to aid in offline instruction rescheduling.
Early IR-drop Analysis Flow for Hot-spot pre-emption.
(2015-07-06) Bhattacharya, Suprio; William Davis, Chair; Paul Franzon, Member; Eric Rotenberg, Member
Efficient Data Dependence Profiling.
(2013-02-08) Vanka, Rajeshwar; James Tuck, Chair; Xiaosong Ma, Member; Huiyang Zhou, Member; Dr. Peter Pirkelbauer, Technical Consultant; Dr. Daniel Quinlan, Technical Consultant; Dr. Greg Bronevetsky, Technical Consultant; Eric Rotenberg, Member
Efficient Hardware Acceleration for Real-time GPU Ray Tracing.
(2026-03-12) Tozlu, Yavuz Selim; Huiyang Zhou, Chair; Eric Rotenberg, Member; Michela Becchi, Member; Xipeng Shen, Member
Exploiting Information Redundancy in the Design of DNA Storage Systems.
(2024-04-26) Volkel, Kevin; James Tuck, Chair; Eric Rotenberg, Member; Michela Becchi, Member; Albert Keung, Member
Exploiting Program Redundancy to Improve Performance, Cost and Power Consumtion in Embedded Systems
(2000-07-19) Larin, Sergei Yurievich; Thomas Conte, Chair; Eric Rotenberg, Member; Edward Davis, Member; Paul Franzon, Member
During the last 15 years embedded systems have grown rapidly in complexity and performance to a point where theynow rival the design challenges of desktop systems. Embedded systems are now targets for contradictory requirements: they are expected to occupy a small amount of physical space (e.g., low package count), be inexpensive, consume low power and be highly reliable. Regardless of the decades of intensive research and development, there are still areas that can promise significant benefits if further researched. One such area is the quality of the data which embedded system operates upon. This includes both code and data segments of an embedded system application. This work presents a unified, compiler-driven approach to solving the redundancy problem. It attempts toincrease the quality of the data stream that embedded systems are operating upon while preserving the original functionality. The code size reduction is achieved by Huffman compressing or tailor encoding the ISA of the original program. The data segment size reduction is accomplished by modified Discrete Dynamic Huffman encoding. This work is the first such study that also details the design of instruction fetch mechanisms for the proposed compression schemes.
Exploring Correlation for Indirect Branch Prediction.
(2012-08-23) Panirwala, Chintan Dipakchandra; Huiyang Zhou, Chair; Eric Rotenberg, Member; Gregory Byrd, Member
Fast and Accurate Event Prediction for System-on-Chip Power and Energy Estimation.
(2023-12-01) Wang, Zhiping; William Davis, Chair; Eric Rotenberg, Member; Huiyang Zhou, Member; Xu Liu, Member; Paul Franzon, Member
General Purpose Intra-Operation Dynamic Voltage Scaling.
(2016-11-04) Moore, Daniel Ross; Alexander Dean, Chair; James Tuck, Member; Eric Rotenberg, Member; Vincent Freeh, Minor
A Generic, Scalable Architecture for a Large Acoustic Model and Large Vocabulary Speech Recognition Accelerator.
(2012-11-12) Bapat, Ojas Ashok; Paul Franzon, Chair; William Davis, Member; Robert Rodman, Member; Eric Rotenberg, Member
GPU Memory Architecture Optimization.
(2017-04-06) Dai, Hongwen; Huiyang Zhou, Chair; Eric Rotenberg, Member; James Tuck, Member; Xipeng Shen, Member