Browsing by Author "George Rouskas, Committee Co-Chair"

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Practical Fair Queuing Schedulers: Simplification through Quantization
(2009-06-30) Dwekat, Zyad; Mladen Vouk, Committee Chair; George Rouskas, Committee Co-Chair; Mihail Sichitiu, Committee Member; Michael Devetsikiotis, Committee Member
Many packet scheduling schemes have been proposed, but most of them suffer from one of two extremes. A scheduling scheme may have simple implementation with low fairness qualities, or it may have good fairness qualities but high complexity. Our goal in this research is to design a frame work of schedulers that has both the desired qualities of fairness and simple implementation. We began our research by conducting a survey of the scheduling techniques and associated analysis models proposed during the last decade. Then, in the first part of this thesis we present a suite of packet fair queuing schedulers with low complexity and good fairness and delay properties. Our designs employ the concept of quantization by exploiting two widely-observed characteristics of the Internet, namely that service providers offer some type of tiered service with a small number of service levels, and that a small number of packet sizes dominate. Taken together, these two observations permit us to design a good fair queuing algorithm in a manner that packet sorting operations only need to consider a small, fixed number of packets, independent of the number of flows, and hence can be performed in constant time. Specifically, the scheduler we present is equivalent to WF2Q, with the additional advantage that the virtual time function can be computed in O(1) time. Our tiered-service schedulers operate under assumptions that are valid under a wide range of practical scenarios, and combine provable good performance with amenability to hardware implementation in high-speed routers. In the second part of this thesis, we use quantization of virtual time to design a novel packet scheduler called Worst-Case Bin Sort Queuing (WBSQ). WBSQ has constant complexity, and can be utilized in a simple hardware implementation. The WBSQ scheduler uses two methods of quantization. First, WBSQ exploits quantization of virtual time in a manner similar to the bin sorting idea in BSFQ [1] scheduler. In addition, WBSQ simplifies the system virtual time implementation of WF2Q+ [2]. Worst-Case Bin Sort Queuing has good worst-case fairness and delay properties that are demonstrated through both analytical results and simulations.
Stack Composition for SILO Architecture
(2008-03-24) Vellala, Manoj; Rudra Dutta, Committee Chair; George Rouskas, Committee Co-Chair; Khaled Harfoush, Committee Member
SILO is a new internetworking architecture that represents a significant departure from current philosophy and practice. The architecture consists of building blocks of fine-grain functionality, explicit support for combining elemental blocks to accomplish highly configurable complex communication tasks, and control elements to facilitate (what is currently referred to as) cross-layer interactions. It takes a holistic view of network design, allowing applications to work synergistically with the network architecture and physical layers so as to meet the application's needs within resource availability constraints. The SILO research advocates a non-layered architecture based on silos of services assembled on demand and specific to an application and network environment. With the goal to facilitate what in today's layered architecture is referred to as 'cross-laye' interactions, in a manner that meets the exact user requirements and optimizes performance, the main focus of this research work is on developing mechanisms to optimize the construction of SILOs (stack of services) in a manner that takes into account service specific constraints, current network conditions and user policies.