Browsing by Author "Jon-Paul Maria, Committee Member"

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Advanced Materials Based on Carbon Nanotube Arrays, Yarns and Papers
(2010-04-20) Bradford, Philip David; Yuntian Zhu, Committee Chair; Jon-Paul Maria, Committee Member; Maurice Balik, Committee Member; Alexander Bogdanovich, Committee Member
Carbon nanotubes have hundreds of potential applications but require innovative processing techniques to manipulate the microscopic carbon dust into useful devices and products. This thesis describes efforts to process carbon nanotubes (CNTs) using novel methods with the goals of: 1) improving the properties of energy absorbing and composite carbon nanotube materials and 2) increasing understanding of fundamental structure â€“ property relationships within these materials. Millimeter long CNTs, in the form of arrays, yarns and papers, were used to produce energy absorbing foams and high volume fraction CNT composites. Vertically aligned CNT arrays were grown on silicon substrates using chemical vapor deposition (CVD) of ethylene gas over iron nano-particles. The low density, millimeter thick arrays were tested under compression as energy absorbing foams. With additional CVD processing steps, it was possible to tune the compressive properties of the arrays. After the longest treatment, the compressive strength of the arrays was increased by a factor of 35 with a density increase of only six fold, while also imparting recovery from compression to the array. Microscopy revealed that the post-synthesis CVD treatment increased the number of CNT walls through an epitaxial type radial growth on the surface of the as-grown tubes. The increase in tube radius and mutual support between nanotubes explained the increases in compressive strength while an increase in nanotube roughness was proposed as the morphological change responsible for recovery in the array. Carbon nanotube yarns were used as the raw material for macroscopic textile preforms with a multi-level hierarchical carbon nanotube (CNT) structure: nanotubes, bundles, spun single yarns, plied yarns and 3-D braids. In prior tensile tests, composites produced from the 3-D braids exhibited unusual mechanical behavior effects. The proposed physical hypotheses explained those effects by molecular level interactions and molecular hindrance of the epoxy chains with individual carbon nanotubes occupying about 40% of the composite volume. Dynamic Mechanical Analysis was used to study the molecular transitions of neat epoxy resin samples and their corresponding CNT yarn composite samples with varying matrix properties. Dramatic effects on the intensity and temperature at which Î±-transitions occurred were recorded, as well as a marked effect on the smaller segmental motions, or Î²-transitions. These changes in the matrix assist in explaining the previously reported tensile property data and the proposed physical explanation of those data. Electrical conductivity of carbon nanotube yarns and hybridized 3-D braided composites consisting of CNT yarns and insulating glass fibers were also investigated. The innovative hybridized structure provided electrical conductivity to the otherwise insulating preforms and composite structures. Finally, a new processing method of â€œshear pressingâ€ was developed to produce CNT buckypapers. Tall aligned carbon nanotube arrays were converted into aligned CNT buckypaper preforms for composite fabrication. These preforms contained the desired characteristics of millimeter long CNTs, high CNT volume fraction, high CNT alignment, small diameter MWNTs and fast processing speed, which have been challenging to achieve simultaneously and are crucial for obtaining the optimum composite tensile properties. Alignment of CNTs in the buckypaper preforms was confirmed through SEM analysis of the shear pressed films in their as-pressed state and of failure surfaces of a tensile specimen. Mechanical properties of the composite were very promising as they were higher than other CNT-epoxy composites with similar volume fractions. Tensile strength of the composites reached 400 MPa. Electrical conductivity of the composites reached 77 S/cm, proving that they may be useful for composite applications where electrical conductivity is important.
Aluminum Nitride Bulk Crystal Growth in a Resistively Heated Reactor
(2005-08-23) Dalmau, Rafael Federico; Jon-Paul Maria, Committee Member; Raoul Schlesser, Committee Member; Robert Nemanich, Committee Member; Zlatko Sitar, Committee Chair
A resistively heated reactor capable of temperatures in excess of 2300°C was used to grow aluminum nitride (AlN) bulk single crystals from an AlN powder source by physical vapor transport (PVT) in nitrogen atmosphere. AlN crystals were grown at elevated temperatures by two different methods. Self-seeded crystals were obtained by spontaneous nucleation on the crucible walls, while seeded growth was performed on singular and vicinal (0001) surfaces of silicon carbide (SiC) seeds. During self-seeded growth experiments a variety of crucible materials, such as boron nitride, tungsten, tantalum, rhenium, tantalum nitride, and tantalum carbide, were evaluated. These studies showed that the morphology of crystals grown by spontaneous nucleation strongly depends on the growth temperature and contamination in the reactor. Crucible selection had a profound effect on contamination in the crystal growth environment, influencing nucleation, coalescence, and crystal morphology. In terms of high-temperature stability and compatibility with the growth process, the best results for AlN crystal growth were obtained in crucibles made of sintered tantalum carbide or tantalum nitride. In addition, contamination from the commercially purchased AlN powder source was reduced by pre-sintering the powder prior to growth, which resulted in a drastic reduction of nearly all impurities. Spontaneously grown single crystals up to 15 mm in size were characterized by x-ray diffraction, x-ray topography, glow discharge mass spectrometry, and secondary ion mass spectrometry. Average dislocation densities were on the order of 10³ cm⁻³, with extended areas virtually free of dislocations. High resolution rocking curves routinely showed peak widths as narrow as 7 arcsec, indicating a high degree of crystalline perfection. Low-temperature partially polarized optical reflectance measurements were used to calculate the crystal-field splitting parameter of AlN, Δ[subscript cr] = -230 meV, and from this, a low-temperature (1.7 K) band gap energy of 6.096 eV was obtained for unstrained wurtzite AlN. Seeded growth of AlN bulk crystals on on-axis and off-axis (0001), Si-face SiC seeds was investigated as a means to scale up maximum single crystal size and pre-define crystal orientation. A two-step deposition process was developed for the growth of thick layers. AlN layers 0.1—3 mm thick were deposited on inch-sized seeds. X-ray diffraction analysis evidenced that the AlN grew in the direction of the seed. A one-dimensional isotropic model was formulated to calculate the thermal stress distribution in AlN/SiC heterostructures. Cracks formed in the AlN layers due to the thermal expansion mismatch between AlN and SiC were observed to decrease with increasing AlN thickness, in agreement with model calculations. Crack-free AlN crystals were obtained from grown layers by evaporating the SiC seed in situ during high-temperature PVT growth. Based on these results, a reproducible seeded growth process was developed for production of crack-free AlN crystals having pre-determined polarity and orientation.
Atomic Layer Deposition on Fiber Forming Polymers and Nonwoven Fiber Structures.
(2010-03-22) Spagnola, Joseph; Mark Johnson, Committee Chair; Gregory Parsons, Committee Member; Ronald Scattergood, Committee Member; Jon-Paul Maria, Committee Member
Coupled Chip-to-Chip Interconnect Design
(2006-12-13) Luo, Lei; Paul D. Franzon, Committee Chair; John M. Wilson, Committee Co-Chair; Michael B. Steer, Committee Member; W. Rhett Davis, Committee Member; Jon-Paul Maria, Committee Member
In modern high performance VLSI chips high bandwidth and high throughput are becoming increasingly important. Multi-Tb⁄s throughput is the current trend of high performance VLSI chips. This trend demands high speed, high density and low power I⁄Os. AC coupled interconnect (ACCI) has been demonstrated as a systematic approach to provide higher pin density, smaller transceiver design and lower power dissipation for high speed chip-to-chip communications. ACCI utilizes non-contact capacitor plates as signal pins which yields a much higher pin density than traditional solder bump pins. The coupling capacitors provide passive equalization, thus eliminating the need for costly traditional active equalization. This saves both power and area associated with the equalization circuitry used in a traditional transceiver. ACCI also saves significant power on the transmitter by using pulse signaling instead of traditional non-return-to-zero (NRZ) signaling The pulse receiver is one of the most important designs in ACCI. The pulse receiver is used at receiver front end to recover the NRZ signal from the small pulse signal. A complementary low swing pulse receiver was designed to allow greater attenuation and to accommodate smaller coupling capacitors and longer transmission lines (T-Lines). A test chip with a complete capacitively coupled serial link was designed; including random data generator, multi-phase DLL, serializer, transmitter, pulse receiver, clock and data recovery (CDR), deserializer and bit error rate (BER) tester. ACCI chip-to-chip communication was demonstrated through two 150fF coupling capacitors and a single end terminated 15 cm microstrip line on a FR4 board at 3Gb⁄s. A differential pulse receiver is proposed for ACCI bus. The design and measurements of the proposed 36Gb⁄s receiver which operated over the 6-bit wide ACCI bus were reported. Signal integrity issues associated with the ACCI bus, such as crosstalk and switching noise, are discussed. Simulation results demonstrated that a higher data rate over ACCI channel can be achieved with more advanced CMOS technologies.
Device Fabrication and Characterization for Alternative Gate Stack Devices
(2003-06-04) Kim, Indong; Carlton M. Osburn, Committee Chair; John R. Hauser, Committee Member; Veena Misra, Committee Member; Jon-Paul Maria, Committee Member
Aggressive scaling has continued to improve MOSFET transistor performance. An effective oxide thickness (EOT) less than 1.0nm is required for future technology nodes. However, tunneling currents of SiO2 become quite prominent below 1.5nm, leading to high leakage current. High-K dielectrics are required to reduce this leakage. A thicker dielectric reduces the probability of electron and/or hole tunneling through the gate dielectric and therefore the tunneling current. The use of metal gate electrodes is one of the technologies assumed in ITRS roadmap to circumvent the high sheet resistance and depletion associated with poly-Si gates. This dissertation covers the following research areas. First, projections of gate leakage currents for future ITRS nodes were made. High-K dielectrics which dramatically lower leakage will be needed for low standby power applications around year 2005. Secondly, NMOS and PMOS devices with alternative gate stacks were fabricated and evaluated using a new non-self aligned process. PVD HfO2 with an equivalent oxide thickness of 1.2 nm had a channel mobility comparable to SiO2. The effect of post metallization annealing of devices having PVD HfO2 was studied. Forming gas (10% H2 / 90% N2) annealing at 400° C enhanced drive current and channel mobility for devices having 1.2nm HfO2 gate dielectrics by eliminating interface states. PMA using 10% deuterium for 1.2nm HfO2 gate dielectrics resulted in larger enhancement drive currents and device channel mobility as compared to forming gas anneals. The stability of poly-Si gated HfO2 (~1.2nm EOT) dielectrics was also assessed after constant current stressing of the gate. The changes in device properties were measured as a function of stress time and stress current. With forming gas annealed HfO2, positive shifts in the threshold voltage exhibited a power law dependence on the injected charge (ΛVt ∝ QINJ 0.1). Finally, the properties of dilute Hf silicate were studied. A leakage minima was found at an intermediate Hf silicate (45~75% HfO2) composition. Nitirdation inhibited oxygen diffusion through Hf silicate dielectrics, and resulted in lower EOTs (10% lower) for nitrided samples.
Engineering of Electrochemically and Optically Active Silica Nanocomposites.
(2010-05-18) Choi, Yong; Tzy-Jiun Luo, Committee Chair; Thomas Pearl, Committee Chair; Donald Brenner, Committee Member; Jon-Paul Maria, Committee Member
Fixed Charge Reduction and Tunneling in Stacked Dielectrics
(2005-07-27) Hinkle, Christopher; Gerald Lucovsky, Committee Chair; Jon-Paul Maria, Committee Member; Robert Nemanich, Committee Member; Hans Hallen, Committee Member
Stacked gate dielectrics using high-k materials were deposited using a RPECVD method. Aluminum oxide, hafnium oxide, hafnium silicate, nitrided films of each of the above, and multi-layer stacks of the above as well as silicon dioxide were deposited. These films were analyzed using AES, XPS, NRA, RBS, SIMS, XAS, cathodoluminescence, spectroscopic ellipsometry, capacitance-voltage, and current-voltage techniques. Fixed charge was found to be present in all high-k films and was practically impossible to reduce in a significant way. Nitridation of the films was unsuccessful at reducing the charge, but was helpful in enhancing some electrical measurements. Sandwich stack structures showed enhanced tunneling which led to a novel approach of calculating the E[subscript b]-m[subscript eff] product in the transmission probability equation. This tunneling also gives some clues as to which types of gate stacks cannot be used in technology. Gate stacks containing an HfO₂ layer below an Al₂O₃ layer were studied and also showed enhanced tunneling. Analysis of this tunneling found two significant trapping sites in the HfO₂ layer, one located ~0.5 eV below the HfO₂ conduction band offset and the other located in the Si bandgap. Fixed charge reduction was again expected in these laminates, but again remained despite theoretical predictions.
Frequency agile RF/microwave circuits using BST varactors
(2004-04-08) Jin, Zhang; Angus Kingon, Committee Member; Jon-Paul Maria, Committee Member; Griff Bilbro, Committee Member; Gianluca Lazzi, Committee Member; Amir Mortazawi, Committee Chair
The research has focused on characterizing barium strontium titanate or BST film at RF/microwave frequencies, improving BST capacitor quality factors and designing frequency agile RF/microwave circuits. A simple and fast measurement technique is developed to extract BST loss tangent and dielectric constant in a parallel plate capacitor. An error analysis is performed to indicate the measurement accuracy. In addition, the BST capacitor layout is optimized to achieve the best possible quality factor. BST capacitor based tunable band-pass filters are designed. Two coupled half-wavelength microstrip resonators are used in the filter. BST capacitors are placed at the end of resonators, which change the filter performance. Analysis shows that with the increase in BST capacitance, the filter skirt sharpness increases, the circuit size decreases, and the tunability increases but the insertion loss increases. Different filter specifications are achieved using various BST capacitances. In addition, a new topology is developed to maintain the 3-dB bandwidth of filters at different biases. The bandwidth change decreases from 54% to only 4% using the new topology. A tunable microstrip antenna is designed, fabricated and measured. Multiple varactors are used to load the rectangular microstrip antenna. A figure of merit is defined to find the optimum number of varactors. Good tunability of 25% and maximum gain of 7.8 dB are achieved within the tuning range. Almost uniform radiation patterns at different biases are also obtained. The measurement results prove that tunable microstrip antennas using multiple varactors loading can achieve better performance than those using single varactor loading. A tunable high impedance surface is designed, fabricated and measured. The surface uses lumped elements to form a parallel resonant circuit. Unlike other lumped-element high impedance surfaces, the inductor in this surface is obtained from the grounded substrate, which shows much higher quality factor and requires less substrate height than those using vias to obtain inductance. Measured tunability of 62% is achieved.
Lanthanide-based Oxides and Silicates for High-K Gate Dielectric Applications
(2007-07-27) Jur, Jesse Stephen; Angus Kingon, Committee Chair; Gregory Parsons, Committee Member; Jon-Paul Maria, Committee Member; Mark Johnson, Committee Member
The ability to improve performance of the high-end metal oxide semiconductor field effect transistor (MOSFET) is highly reliant on the dimensional scaling of such a device. In scaling, a decrease in dielectric thickness results in high leakage current between the electrode and the substrate by way of direct tunneling through the gate dielectric. Observation of a high leakage current when the standard gate dielectric, SiO2, is decreased below a thickness of 1.5 nm requires engineering of a replacement dielectric that is much more scalable. This high- dielectric allows for a physically thicker oxide, reducing leakage current. Integration of select lanthanide-based oxides and silicates, in particular lanthanum oxide and silicate, into MOS gate stack devices is examined. The quality of the high-K dielectrics is monitored electrically to determine properties such as equivalent oxide thickness, leakage current density and defect densities. In addition, analytical characterization of the dielectric and the gate stack is provided to examine the materialistic significance to the change of the electrical properties of the devices. It is shown that optimization of low-temperature processing can result in MOS devices with an equivalent oxide thickness (EOT) as low 5 Å and a leakage current density of 5.0 A⁄cm2. High-temperature processing, consistent with a MOSFET source-drain activation anneal, yields MOS devices with an EOT as low as 1.1 nm after optimization of the TaN/W electrode properties. The decrease in the device effective work function (phi_M,eff) observed in these samples is examined in detail. First, as a La2O3 capping layer on HfSiO(N), the shift yields ideal-phi_M,eff values for nMOSFET deices (4.0 eV) that were previously inaccessible. Other lanthanide oxides (Dy, Ho and Yb) used as capping layers show similar effects. It is also shown that tuning of phi_M,eff can be realized by controlling the extent of lanthanide-silicate formation. This research, conducted in conjunction with SEMATECH and the SRC, represents a significant technological advancement in realizing 45 and sub-45 nm MOSFET device nodes.
Properties of Zr Silicate and Zr-Si Oxynitride High-k Dielectric Alloys for Advanced Microelectronic Applications; Chemical and Electrical Characterizations
(2005-09-27) Ju, Byongsun; Gerald Lucovsky, Committee Chair; Jon-Paul Maria, Committee Member; Robert Nemanich, Committee Member; Carl Osburn, Committee Member
As the microelectronic devices are aggressively scaled down to the 1999 International Technology Roadmap, the advanced complementary metal oxide semiconductor (CMOS) is required to increase packing density of ultra-large scale integrated circuits (ULSI). However, SiO2 or Si oxynitride (SiOxNy) films which is a traditional gate oxide materials shows its limitations in direct tunneling current density at the below about 3nm thickness, and moreover, the priority of leakage current is ranked high in device performance and reliability as the portable device prevails. High-k alternative dielectrics can provide the required levels of EOT for device scaling at larger physical thickness, thereby providing a materials pathway for reducing the tunneling current. Zr silicates and its end members (SiO2 and ZrO2) and Zr-Si oxynitride films, (ZrO2)x(Si3N4)y(SiO2)z, have been deposited using a remote plasma-enhanced chemical vapor deposition (RPECVD) system. After deposition of Zr silicate, the films were exposed to He/N2 plasma to incorporate nitrogen atoms into the surface of films. The amount of incorporated nitrogen atoms was measured by on-line Auger electron spectrometry (AES) as a function of silicate composition and showed its local minimum around the 30% silicate. Characterization by AES and x-ray photoelectron spectroscopy (XPS) indicated that the nitrogen atoms were substituted for the oxygen atoms' position and made a bond with Si and Zr depending on the silicate composition. The effect of nitrogen atoms on capacitance-voltage (C-V) and leakage-voltage (J-V) were also investigated by fabricating metal-oxide-semiconductor (MOS) capacitors. Results suggested that incorporating nitrogen into silicate decreased the leakage current in SiO2-rich silicate, whereas the leakage increased in the middle range of silicate. The pseudo-ternary alloy composition was determined by Rutherford back scattering (RBS) that was calibrated by on-line Auger electron spectroscopy (AES) and showed the composition's thermodynamically stable boundary composition in ternary phase diagrams. Zr-Si oxynitride was a pseudo-ternary alloy and no phase separation was detected by x-ray photoelectron spectroscopy (XPS) analysis up to 1100°C annealing. The leakage current of Zr-Si oxynitride films showed two different temperature dependent activation energies, 0.02 eV for low temperature and 0.3 eV for high temperature. Poole-Frenkel emission was the dominant leakage mechanism. Zr silicate alloys with no Si3N4 phase were chemically separated into the SiO2 and ZrO2 phase as annealed above 900°C. While chemical phase separation in Zr silicate films with Si3N4 phase (Zr-Si oxynitride) were suppressed as increasing the amount of Si3N4 phase due to the narrow bonding network in Si3N4 phase. (3.4 bonds/atom for Si3N4 network, 2.67 bonds/atom for SiO2 network)
Spectroscopic Study of the Interface Chemical and Electronic Properties of High-kappa Gate Stacks
(2005-08-11) Fulton, Charles Clifton; Jon-Paul Maria, Committee Member; Angus I Kingon, Committee Member; Robert J Nemanich, Committee Chair; Gerald Lucovsky, Committee Member
X-ray and ultraviolet photoemission spectroscopy has been combined with in-situ deposition to study the interface chemistry and electronic structure of potential high-κ gate stack materials. In addressing the interface stability of ZrO2 with respect to a Si substrate three issues are considered: 1) the development of the band offsets and electronic structure during the low temperature (T<300°C) growth processes, 2) variations in the band structure as effected by process conditions and annealing (T<700°C) and 3) the interface stability of Zr oxide films at high temperatures (T>700°C). To further explore low temperature effects, titanium, zirconium and hafnium oxides were deposited on ultra-thin (~0.5 nm) SiO2 buffer layers and metastable states have been identified which give rise to large changes in the band alignments with respect to the Si substrate. Also discussed is the band edge electronic structure of 1) nanocrystalline Zr, Hf and complex oxide high-κ dielectrics, and 2) non-crystalline Zr and Hf silicates and Si oxynitride alloys. Three issues are highlighted: Jahn-Teller term-splittings that remove band edge d-state degeneracies in nanocrystalline films, intrinsic bonding defects in ZrO2 and HfO2, and chemical phase separation and crystallinity in Zr and Hf silicate and Si oxynitride alloys. Finally, photoemission spectroscopy has been used to characterize a candidate gate stack including electron affinities and work functions, valence band maxima, band bending in the Si and fields in the oxide layers. The band offsets are constructed and the deviation from the Schottky-Mott (or electron affinity) model at each interface is discussed in terms of interface bonding and the resultant charge transfer.
Theoretical and Experimental Spectroscopic studies of Conducting Metal Oxide Thin Films
(2009-08-20) Efremenko, Alina Yurievna; Stefan Franzen, Committee Chair; Lin He, Committee Member; Jon-Paul Maria, Committee Member
In order to expand on the growing field on Surface Plasmon Resonance Spectroscopy (SPRS) the application of SPRS to Conducting Metal Oxides (CMO) was studied. Through experimental and theoretical studies it was concluded that CMOÃ¢â‚¬â„¢s are capable of sustaining Surface Plasmon Polaritons (SPP) like those in noble metals. Specifically, we have used indium tin oxide (ITO) as a test case to demonstrate the interplay of experiment and theory. Theoretical studies provided an excellent basis for comparison to experimental data. Furthermore, Near Edge X-Ray Absorption Fine Structure Spectroscopy (NEXAFS) was applied in order to examine the ITO as a substrate for self assembled monolayers (SAMs). It was found that hexadecanethiol and phosphonic acid form ordered monolayers on ITO.