Browsing by Author "Mark Johnson, Committee Member"

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Amorphous Indium Gallium Zinc Oxide Thin-Film Transistors, Non-volatile Memory and Circuits for Transparent Electronics
(2010-06-26) Suresh, Arun; Leda lunardi, Committee Member; Mark Johnson, Committee Member; Veena Misra, Committee Member; John Muth, Committee Chair
The ability to make electronic devices, that are transparent to visible and near infrared wavelength, is a relatively new field of research in the development of the next generation of optoelectronic devices. A new class of inorganic thin-film transistor (TFT) channel material based on amorphous oxide semiconductors, that show high carrier mobility and high visual transparency, is being researched actively. The purpose of this dissertation is to develop amorphous oxide semiconductors by pulsed laser deposition, show their suitability for TFT applications and demonstrate other classes of devices such as non-volatile memory elements and integrated circuits such as ring oscillators and active matrix pixel elements. Indium gallium zinc oxide (IGZO) is discussed extensively in this dissertation. The influence of several deposition parameters is explored and oxygen partial pressure during deposition is found to have a profound effect on the electrical and optical characteristics of the IGZO films. By optimizing the deposition conditions, IGZO TFTs exhibit excellent electrical properties, even without any intentional annealing. This attribute along with the amorphous nature of the material also makes IGZO TFTs compatible with flexible substrates opening up various applications. IGZO TFTs with saturation field effect mobility of 12 â€“ 16 cm2 V-1 s-1 and subthreshold voltage swing of < 200 mV decade-1 have been fabricated. By varying the oxygen partial pressure during deposition the conductivity of the channel was controlled to give a low off-state current ~ 10 pA and a drain current on/off ratio of > 1 x108. Additionally, the effects of the oxygen partial pressure and the thickness of the semiconductor layer, the choice of the gate dielectric material and the device channel length on the electrical characteristics of the TFTs are explored. To evaluate IGZO TFT electrical stability, constant voltage bias stress measurements were carried out. The observed logarithmic dependence of the threshold voltage shift to the stress duration was modeled using a charge trapping/tunneling mechanism at the semiconductor/dielectric interface. By incorporating platinum nanoparticles in the dielectric layer of the TFT, non-volatile memory characteristics were achieved. The devices exhibited good memory behavior and up to 10 % charge retention extrapolated over 10 years. The potential application for IGZO TFTs is examined by fabricating and characterizing 5- and 7-stage ring oscillators. The 5-stage ring oscillators operate at more than 2 MHz and have a sub 50 ns propagation delay at a supply voltage of 25 V. To the best of our knowledge these are the fastest all-transparent ring oscillators reported to date. As a practical demonstration, we integrated IGZO TFTs with a novel thin film electroluminescent phosphor to form an active matrix pixel element. The output intensity of the phosphor was successfully modulated by the TFT. These results demonstrate that IGZO TFTs are viable candidates for transparent circuits and display applications.
The Chemical Solution Deposition of Lead Zirconate Titanate (PZT) Thin Films Directly on Copper Surfaces
(2005-07-13) Losego, Mark Daniel; Mark Johnson, Committee Member; Gerry Lucovsky, Committee Member; Jon-Paul Maria, Committee Chair
Traditionally, multifunctional complex oxide thin films, like the common ferroelectric materials lead zirconate titanate (PZT) and barium titanate (BaTiO₃) have been limited to substrates with noble metal or conductive oxide bottom electrodes. This constraint originates from the vulnerability of base metals to oxidation when traditional ceramic processing parameters—high temperatures and oxygen rich atmospheres—are used to synthesize ferroelectric films. With current technology, ferroelectric thin films have demonstrated vast applicability as tunable capacitors, sensors, piezoelectric actuators, and non-volatile memories. By integrating ferroelectrics thin films with base metals, the barrier to mass production is lowered through reduced expense and simplified electrode patternability. Moreover, base metals have higher conductivities and offer the possibility for increased functionality by incorporation of ferromagnetic or shape memory alloys. Recent research efforts have adapted 1970s thick film multilayer capacitor technology to process thin films of the (Ba,Sr)TiO₃ family directly on nickel and copper substrates. This methodology relies on processing these materials within a window of temperature and oxygen partial pressure (pO₂) that affords thermodynamic equilibrium between the oxidized perovskite film and unoxidized base metal substrate. Although the family of (Ba,Sr)TiO₃ materials offers excellent dielectric properties, the material PZT could provide a complementary set of functionality to satisfy applications that require an enhanced ferroelectric or piezoelectric response. Unfortunately, fundamental materials differences—particularly PbO volatility and a narrow thermodynamic stability window—make equilibrium processing impractical for PZT/base metal systems. In this thesis, integration of PZT directly on copper surfaces via a chemical solution deposition (CSD) route is investigated. Using this platform a new methodology is developed for achieving perovskite / base metal compatibility. Unlike the traditional equilibrium approach, this new method focuses on using a knowledge of sol-gel science to design a process window that is compatible with the copper substrate while maintaining the integrity of the PZT film. Using this approach, the chelating ligands (organic molecules that impart stability to the metal cations in solution) have been identified as a critical process parameter. If these chelating species cannot provide sufficient gel consolidation and volatilization prior to crystallization within a processing window compatible with the copper substrate, then various complications can result such as substrate oxidation, non-perovskite phase development, or film cracking. By proper chelating agent selection and a unique composite gel architecture, this thesis demonstrates that PZT films can be processed directly on copper substrates with dielectric and ferroelectric properties comparable to films deposited on conventional platinized silicon. Dielectric constants in excess of 800 with tanδ values below 0.02 have been achieved as well as remanent polarization of 33 μC/cm². C-V and P-E loops exhibit classical ferroelectric shapes with well-saturated intrinsic regimes. Electrical fatigue experiments show a classic response with loss of P-E loop squareness and a recoverable remanent polarization upon annealing above the Curie point. Hence, this work demonstrates a methodology for obtaining PZT thin films on copper substrates with remarkable dielectric and ferroelectric properties that are competitive with current noble metal / conductive oxide bottom metal electrode technologies.
The Chemistry and Surface Microstructure of Si-Based Substrates and their Effect on the Evolution of the Microstructures of III-Nitride Films Grown via Metalorganic Vapor Phase Epitaxy
(2005-03-31) Reitmeier, Zachary J; Robert F. Davis, Committee Chair; Zlatko Sitar, Committee Member; Mark Johnson, Committee Member; John Muth, Committee Member
The present research was undertaken with the goals of understanding the evolution of defects and strain in heteroepitaxial AlN and GaN films deposited via metalorganic vapor phase epitaxy and minimizing those defects through manipulation of the substrate. As observed with atomic force microscopy (AFM), AlN initially grew in the form of flat-topped islands on as-received SiC substrates. Threading dislocations (TDs) observed in transmission electron microscopy (TEM) images initiated at the AlN/SiC interface as the result of defects at the surface of the mechanically polished substrate and/or condensation of point defects. GaN initially grew in the Stranski-Krastanov mode on AlN/SiC before transitioning to the dislocation-mediated step flow mode. The TDs in GaN resulted from the propagation of the TDs present in the AlN layer. The biaxial strain in the GaN layers varied with buffer layer material and layer thickness yet all samples investigated remained in residual compression due to incomplete relaxation of the coherent strain. The presence of strain during the initial growth of Al[subscript x]Ga[subscript 1-x]N layers directly on as-received SiC also resulted in phase-separated regions of Al-rich and Al-poor film. A high temperature hydrogen etch was then used to remove mechanical polishing scratches from the SiC substrates. Subsequently deposited AlN layers featured reduced pit density and the elimination of scratch-induced undulations. GaN layers deposited with AlN buffer layers on these substrates resulted in slightly reduced TD densities as observed by AFM, TEM, and high resolution X-ray diffraction (HRXRD). Regions of dramatically reduced dislocation densities were observed by HRXRD, TEM, and cathodoluminescence for GaN layers on stripe-patterned Si substrates. However, long growth times resulted in outdiffusion of Si from the substrate and subsequent film roughening. Finally, it was demonstrated that the presence of ammonia during heating of GaN templates to the growth temperature for homoepitaxy resulted in removal of carbon- and oxygen-based contaminants from the template surface.
Electron Transport in Bulk-Si NMOSFETs in Presence of High-k Insulator-charge Trapping and Mobility
(2006-11-29) Maitra, Kingsuk; Mark Johnson, Committee Member; Douglas Barlage, Committee Member; Carl Osburn, Committee Member; Veena Misra, Committee Chair
Recent advancements in gate stack engineering has led to the development of aggressively scaled, high mobility, high-k dielectric based NMOSFETs with metal gates. Most of the current literature on the subject also stressed on the need for a high temperature process step to attain the high mobility under minimal change of effective oxide thickness. However, the physical origin of high mobility is not well understood. In this work, fundamental insight into the necessity of the high temperature process step is provided. Novel experimental strategies are developed to understand the impact of interface states and bulk traps separately and exclusively on channel mobility. It is conjectured that the interface states at the SiO2⁄(100) bulk-Si interface are identical in nature (as far as coupling with the channel electrons is concerned) to those at the high-k⁄SiO2⁄(100) bulk-Si interface. Thus, the response of interface states on channel electrons in high-k insulator based NMOSFETs is properly calibrated by a novel thermal desorption of hydrogen experiment on SiO2⁄(100) bulk-Si NMOSFETs to yield a highly accurate parameterized equation. The value of interface state response parameter determined by the aforementioned experiment is compared with theoretical predictions, and independently determined projections from electrical stress measurements. The impact of transient charging on transport in the channel is investigated. It is conclusively shown that remote charge has minimal impact on mobility in the channel. The role of nitrogen induced fixed oxide charge is studied on a set of Hf-silicate samples. Role of soft optical phonon scattering and the beneficial impact of metal gates on soft optical phonon limited mobility are thoroughly investigated both theoretically and experimentally. Conclusions are drawn on the fundamental limit of mobility attainable in high-k dielectric based NMOSFETs.
Electronic Structure Calculations of Bi2Te3/Sb2Te3 Superlattices for Thermoelectric Applications
(2009-11-13) Krishnan, Mandayam Gomatam; Wengchang Lu, Committee Member; Marco Buongiorno Nardelli, Committee Member; Mark Johnson, Committee Member; Michael Paesler, Committee Member
The electronic structure of Bi2Te3/Sb2Te3/BiSbTe3 in quintuple layers is calculated at the atomic level for applications in thermo electric applications of micro refrigeration and power generation. The trigonal lattice structure is used for these combinations of materials in bulk and the hexagonal lattice approximation is used for quintuple layers of these materials (Te1- Bi-Te2-Bi-Te1) for super-lattice structures. Electronic Structure Calculations on various combinations of alternating quintuple layers (1:1, 1:2, 2:1, 1:3, 3:1, 1:4, 2:3, 3:2) are made using Local Density Approximations (LDA) for band gaps and charge distributions and the results compare well with other published methods such as Linearized Augmented Plane Waves (LAPW) used as a reference. The results for (2:1, 1:3, 3:1, 1:4, 2:3, 3:2) super lattices are new for this work without any references.
Epitaxial Oxide Growth on Si(001) for Floating Epitaxy, a Novel Process for Silicon-on-Insulator Wafer Production
(2007-03-08) Hydrick, Jennifer Marie; Angus Kingon, Committee Chair; Veena Misra, Committee Member; Mark Johnson, Committee Member
As scaling continues in the semiconductor industry, silicon-on-insulator (SOI) wafers are increasingly becoming the substrate of choice, due to higher channel mobility, effective device isolation, reduced short channel effects, minimized parasitic capacitance, and therefore higher speed, compared to a regular silicon wafer. Current methods of SOI wafer production, however, will have difficulty achieving the desired silicon device layer and buried oxide insulator layer thicknesses and eliminating interface roughness as scaling proceeds. We propose "Floating Epitaxy SOI" as a novel method of SOI production utilizing an all in-situ growth process. Floating Epitaxy SOI involves Molecular Beam Epitaxy deposition of an epitaxial template oxide, oxidizing through the epitaxial template layer to establish the insulation layer, and silicon growth on top of the epitaxial template oxide layer (which is now "floating" on top of an amorphous oxide layer). The key to this process is the epitaxial oxide template layer, which must deposit on the silicon substrate as an atomically smooth film with a lattice parameter close to that of silicon and must be sufficiently stable in both an oxygen an in vacuum annealing to relatively high temperature to achieve Floating Epitaxy SOI. Although many researchers have examined epitaxial oxides on silicon, this study focuses on epitaxial films over large area substrates, while virtually all other studies report on growth on small substrate sizes. Also, the oxide stability limits on silicon in vacuum have not been thoroughly established by previous work, and are investigated here. The growth and thermal stability of this epitaxial oxide template layer are discussed, as well as brief results for through-oxidation "floating" of the template oxide layer and silicon growth experiments. BaO, SrO, CaO, Ba[subscript 1-x]Sr[subscript x]O, SrTiO₃, CaTiO₃, and Ca[subscript 1-x]Sr[subscript x]TiO₃ were successfully epitaxially deposited on Si(001) substrates. A 64:36 Ba:Sr ratio was used for the solid solution of Ba[subscript 1-x]Sr[subscript x]O, in order to achieve close lattice matching with silicon; a 50:50 Ca:Sr ratio was used initially for the Ca[subscript 1-x]Sr[subscript x]TiO₃ solid solution, an attempt to mediate SrTiO₃'s 2% lattice mismatch with silicon and CaTiO₃'s orthorhombic structure. Alloying SrTiO₃ with calcium to alter the lattice parameter has not been studied much to this point in thin films, and this is the first demonstration of Ca[subscript 1-x]Sr[subscript x]TiO₃ and CaTiO₃ thin films grown directly on silicon. Reflection High Energy Electron Diffraction patterns of both Ba[subscript 1-x]Sr[subscript x]O and Ca[subscript 1-x]Sr[subscript x]TiO₃ indicated high quality 2D epitaxial films. A thin (3 monolayer) film of Ba[subscript 1-x]Sr[subscript x]O is stable on silicon to 535°C in vacuum, while a 5 monolayer Ca[subscript 1-x]Sr[subscript x]TiO₃ film survives to 740°C in vacuum, but roughens from a 2D toward a 3D surface above ˜650°C. Of the epitaxial oxides studied, the solid solution Ca[subscript 1-x}Sr[subscript x]TiO₃ would be the best choice for Floating Epitaxy SOI, based on epitaxial growth quality and stability. High-resolution TEM indicates the presence of an amorphous interfacial layer at the SrTiO₃Si interface, as grown. X-ray diffraction confirms an epitaxial film, with a lattice parameter larger than that of bulk SrTiO₃, likely due to oxygen deficiency in the film. Annealing 17.5nm SrTiO₃Si(001) at 800°C in 5.5 Torr of oxygen for 30 minutes results in an equivalent oxide thickness of 10.3nm, sufficient for scaling to 2020. X-ray diffraction after annealing reveals a still-epitaxial SrTiO₃ film, with sharper 2θ and χ peaks and a lattice parameter closer to that of bulk SrTiO₃. These results validate the "floating" epitaxy approach: an epitaxial film remains on top of an amorphous insulator, after through-oxidation of the substrate. Direct deposition of epitaxial silicon on Ca[subscript 1-x]Sr[subscript x]TiO₃ and solid-phase epitaxy of silicon on a CaTiO₃ film are promising, but interface engineering or a surfactant may be required to achieve a high quality, single crystal silicon layer.
Four Terminal Gallium Nitride MOSFETs.
(2010-12-21) Veety, Matthew; Leda Lunardi, Committee Chair; Douglas Barlage, Committee Chair; Robert Kolbas, Committee Member; Mark Johnson, Committee Member
Gallium Nitride (GaN) Heterogeneous Source Drain MOSFET
(2008-05-18) Ma, Lei; John Muth, Committee Member; Leda Lunardi, Committee Member; Mark Johnson, Committee Member; Doug Barlage, Committee Chair
GaN MOSFETs for Low Power Giga Scale LSI Logic
(2007-07-07) Zeng, Chang; Doug W. Barlage, Committee Chair; John F. Muth, Committee Member; Mark Johnson, Committee Member; Leda Lunardi, Committee Member; Robert M kolbas, Committee Member
Advances in material quality and device processing have led to promising results for III-nitride electronic devices for high frequency applications. Numerous groups have report that GaN metal semiconductor field effect transistors (MESFETs) exhibit excellent device characteristics. However, a major concern of such devices is the leakage from the Schottky gate. As an alternative, the use of an insulated gate metal oxide semiconductor (MOS) structure reduces both gate leakage and power consumption. As described in this work, there are more potential advantages than reduced leakage by adopting a MOS structure in the III-N system. The scalability of this prototype device is shown with simulation to have the potential to support gate lengths below 10nm. In this Dissertation, methods to demonstrate a unique GaN based NMOS devices with minimum gate length of 0.7μm are described. Significant progress has been made on this challenging problem. The goal of this research is to introduce the processing methods and structures that will be suitable as a test vehicle for evaluating material interfaces in the GaN-Ga2O3-gate dielectric system. One of the aspects of this work is that a multi-wafer sapphire to device process time is less than one month. That enables the capacity to evaluate novel deposition schemes through electrical measurements in a timely manor. Furthermore, the process described here integrates re-grown GaN contacts. The pursuit of this is to allow maximum dopant incorporation and maximum abruptness in the source drain region to maximize the transistor's cut off frequency performance as well as the critical Ion performance. This process flow is also established as way to study hetero-geneous source drain properties. A method to analyze the n-i-n structure is presented in some detail. This n-i-n structure, along with the gate oxide, is the secondary key component to demonstrating a GaN MOS transistor with competitive performance properties for digital and RF applications. Of significance is the ability to fabricate a MOS device centered around the re-growth of N-type III-N material on intrinsically doped GaN. This method is directly related to the overall research goal to achieve a compound semiconductor MOSFET suitable for scaling below 10nm. This initial challenge of establishing a suitable experimentation vehicle has been met by the work described in this thesis. The intention of this work is to provide the experimental framework for the exploration of a variety of materials required to synthesize a complimentary GaN MOS system suitable for scaling to dimensions below 10nm.
Growth and Characterization of GaN and AlGaN Thin Films and Heterostructures and the Associated Development and Evaluation of Ultraviolet Light Emitting Diodes
(2005-06-28) Park, Ji-Soo; John Muth, Committee Member; Mark Johnson, Committee Member; Robert F. Davis, Committee Chair; Robert Nemanich, Committee Member
AlGaN-based thin film heterostructures have been grown and fabricated into ultraviolet light emitting diodes with and without p-type and/or n-type AlGaN carrier-blocking layers at the top and the bottom of the quantum wells, respectively, and having the principal emission at 353 nm. The highest values of this peak intensity and light output power were measured in the devices containing p-type carrier-blocking layers. Growth of an n-type carrier-blocking layer had an adverse effect on these device characteristics. A broad peak centered at ~540nm exhibited yellow luminescence and was present in the spectra acquired from all the devices. This peak is attributed to absorption of the ultraviolet emission by and re-emission from the p-GaN and/or to the luminescence from the AlGaN within quantum wells by current injection. Individual AlxGa1-xN films (x<0<1) have been grown on Si- and C-terminated 6H-SiC{0001} substrates and characterized for electron emission applications. The large range in the values of x was achieved by changing the fraction of Al in the gas phase from 0 to 0.45. The ionized donor concentration in the n-type, Si-doped AlxGa1-xN films decreased as the mole fraction of Al was increased due to the reduction in the donor energy level and compensation. The use of the SiH4 flow rate, which yields a Si concentration of ~1E19 cm-3 in GaN, established the upper limit of the mole fraction of Al wherein n-type doping could be achieved at ~0.61. The electron affinity of the Si-doped Al0.61Ga0.39N films was as low as 0.1 eV. Increasing the Si doping concentration in AlN films to as high as 1E21cm-3 caused slight degradation in crystal perfection. No difference was found in the Al core level binding energies between undoped and Si-doped AlN films. The results of XPS and UPS experiments showed that the work function of N-polar AlN films was 0.6 eV lower than that of Al-polar films.
High-Frequency FET Modeling in GaN with Dispersion Effects
(2008-09-18) Morgensen, Michael; Mark Johnson, Committee Member; Kevin Gard, Committee Member; Doug Barlage, Committee Chair
Interfacing Epitaxial Oxides to Gallium Nitride
(2008-08-19) Losego, Mark Daniel; Jon-Paul Maria, Committee Chair; Mark Johnson, Committee Member; Zlatko Sitar, Committee Member; Gregory Parsons, Committee Member
Molecular beam epitaxy (MBE) is lauded for its ability to control thin film material structures at the atomic level. Controlling the chemistry and structure of epitaxial interfaces at the atomic level can improve performance of microelectronics and cultivate the development of novel device structures. This thesis explores the utility of MBE for designing interfaces between oxide epilayers and the wide band gap semiconductor gallium nitride (GaN). The allure of wide gap semiconductor microelectronics (like GaN, 3.4 eV) is their ability to operate at higher frequencies, higher powers, and higher temperatures than current semiconductor platforms. Heterostructures between ferroelectric oxides and GaN are also of interest for studying the interaction between GaN's fixed polarization and the ferroelectric's switchable polarization. Two major obstacles to successful integration of oxides with GaN are: (1) interfacial trap states; and (2) small electronic band offsets across the oxide / nitride interface due to the semiconductor's large band gap. For this thesis, epitaxial rocksalt oxide interfacial layers (˜8 eV band gap) are investigated as possible solutions to overcoming the challenges facing oxide integration with GaN. The cubic close-packed structure of rocksalt oxides forms a suitable epitaxial interface with the hexagonal close-packed wurtzite lattice of GaN. Three rocksalt oxide compounds are investigated in this thesis: MgO, CaO, and YbO. All are found to have a (111) MO || (0001) GaN; <1`10> MO || <11`20> GaN epitaxial relationship. Development of the epilayer microstructure is dominated by the high-energy polar growth surface (drives 3D nucleation) and the interfacial symmetry, which permits the formation of twin boundaries. Using STEM, strain relief for these ionicly bonded epilayers is observed to occur through disorder within the initial monolayer of growth. All rocksalt oxides demonstrate chemical stability with GaN to >1000°C. Concurrent MBE deposition of MgO and CaO is known to form complete solid solutions. By controlling the composition of these alloys, the oxide's lattice parameter can be engineered to match GaN and reduce interfacial state density. Compositional control is a universal challenge to oxide MBE, and the MgO-CaO system (MCO) is further complicated by magnesium's high volatility and the lack of a thermodynamically stable phase. Through a detailed investigation of MgO's deposition rate and subsequent impact on MCO composition, the process space for achieving lattice-matched compositions to GaN are fully mapped. Lattice-matched compositions are demonstrated to have the narrowest off-axis rocking curve widths ever reported for an epitaxial oxide deposited directly on GaN (0.7° in f-circle for 200 reflection). Epitaxial deposition of the ferroelectric (Ba,Sr)TiO3 by hot RF sputtering on GaN surfaces is also demonstrated. Simple MOS capacitors are fabricated from epitaxial rocksalt oxides and (Ba,Sr)TiO3 layers deposited on n-GaN substrates. Current-voltage measurements reveal that BST epilayers have 5 orders of magnitude higher current leakage than rocksalt epilayers. This higher leakage is attributed to the smaller band offset expected at this interface; modeling confirms that electronic transport occurs by Schottky emission. In contrast, current transport across the rocksalt oxide ⁄ GaN interface occurs by Frenkel-Poole emission and can be reduced with pre-deposition surface treatments. Finally, through this work, it is realized that the integration of oxides with III-nitrides requires an appreciation of many different fields of research including materials science, surface science, and electrical engineering. By recognizing the importance that each of these fields play in designing oxide ⁄ III-nitride interfaces, this thesis has the opportunity to explore other related phenomena including accessing metastable phases through MBE (ytterbium monoxide), spinodal decomposition in metastable alloys (MCO), how polar surfaces grown by MBE compensate their bound surface charge, room temperature epitaxy, and the use of surface modification to achieve selective epitaxial deposition (SeEDed growth).
Investigation of MOS Interfaces with Atomic-Layer-Deposited High-k Gate Dielectrics on III-V Semiconductors.
(2010-08-06) Suri, Rahul; Veena Misra, Committee Chair; Mark Johnson, Committee Member; Salah M. Bedair, Committee Member; Mehmet Ozturk, Committee Member; Dan Lichtenwalner, Committee Member
Lanthanide-based Oxides and Silicates for High-K Gate Dielectric Applications
(2007-07-27) Jur, Jesse Stephen; Angus Kingon, Committee Chair; Gregory Parsons, Committee Member; Jon-Paul Maria, Committee Member; Mark Johnson, Committee Member
The ability to improve performance of the high-end metal oxide semiconductor field effect transistor (MOSFET) is highly reliant on the dimensional scaling of such a device. In scaling, a decrease in dielectric thickness results in high leakage current between the electrode and the substrate by way of direct tunneling through the gate dielectric. Observation of a high leakage current when the standard gate dielectric, SiO2, is decreased below a thickness of 1.5 nm requires engineering of a replacement dielectric that is much more scalable. This high- dielectric allows for a physically thicker oxide, reducing leakage current. Integration of select lanthanide-based oxides and silicates, in particular lanthanum oxide and silicate, into MOS gate stack devices is examined. The quality of the high-K dielectrics is monitored electrically to determine properties such as equivalent oxide thickness, leakage current density and defect densities. In addition, analytical characterization of the dielectric and the gate stack is provided to examine the materialistic significance to the change of the electrical properties of the devices. It is shown that optimization of low-temperature processing can result in MOS devices with an equivalent oxide thickness (EOT) as low 5 Å and a leakage current density of 5.0 A⁄cm2. High-temperature processing, consistent with a MOSFET source-drain activation anneal, yields MOS devices with an EOT as low as 1.1 nm after optimization of the TaN/W electrode properties. The decrease in the device effective work function (phi_M,eff) observed in these samples is examined in detail. First, as a La2O3 capping layer on HfSiO(N), the shift yields ideal-phi_M,eff values for nMOSFET deices (4.0 eV) that were previously inaccessible. Other lanthanide oxides (Dy, Ho and Yb) used as capping layers show similar effects. It is also shown that tuning of phi_M,eff can be realized by controlling the extent of lanthanide-silicate formation. This research, conducted in conjunction with SEMATECH and the SRC, represents a significant technological advancement in realizing 45 and sub-45 nm MOSFET device nodes.
Metal alloys and Gate Stack Engineering for CMOS Gate Electrode Application
(2006-10-24) Chen, Bei; D. W. Barlage, Committee Member; Mark Johnson, Committee Member; Veena Misra, Committee Chair; Carl Osburn, Committee Member
The purpose of this research has been to search for proper metallic gate electrodes for CMOS devices. This dissertation covers several binary alloy metal gate research topics. First, intermetallic binary alloy RuY was investigated. From C-V analysis we obtained the effective work function of Ru-Y thin films to range from 5.0eV to 3.9eV which is suitable for dual metal gate CMOS. The rich Y film was found to be not stable on SiO2 dielectrics because of the high oxygen affinity of Y. RuxYy thin film may still be a candidate for low temperature process, especially due to its large range of work function. More over, RuY has smaller grain size than Ru which demonstrates one of the advantages of alloy by reducing grain size to achieve more uniform gate film and more uniform effective work function for the nano-size device applications. Chapter 3 presents MoxTay as a potential candidate for dual metal CMOS applications. The electrical characterization results of MoTa alloy indicates that the effective work function can be controlled to around 4.3 eV on SiO2 and is suitable for NMOS gate electrode application. The MoTa alloy forms a solid solution instead of an intermetallic compound. We report that the MoTa solid solution can achieve low work function values and is stable up to 900°C. X-ray diffraction results indicated only a single MoTa alloy phase. Moreover, from Auger electron spectroscopy and Rutherford backscattering spectroscopy analysis, MoTa was found to be stable on SiO2 under high temperature anneals and no metal diffusion into substrate Si channel was detected. This indicates that MoxTay is a good candidate for CMOS metal gate applications. Chapter 4 evaluates Ru and W capping layer for MoTa metal gate electrodes in Metal Oxide Semiconductor capacitor applications. We report that the oxygen diffusion from the capping layer plays an important role in determining the MoTa alloy effective work function value on SiO2. MoTa alloy metal gate with Ru capping exhibit stable effective work function up to 900°C anneal but is not stable with W capping. Auger electron spectroscopy and Rutherford backscattering spectroscopy analysis shows minimal oxygen diffusion into the MoTa gate stacks with Ru capping while severe oxygen diffusion into the gate is observed with W capping metal after 900°C anneal. In chapter 5, We have studied the φm behavior of AlTa alloys with varying compositions ranging from pure Al to pure Ta. The effective work function of AlTa alloy increased up to 4.45 eV as compared to pure Al work function (~4.1eV) or pure Ta work function (~4.2eV) on SiO2 at 400°C FGA. We ascribe the φm increase due to an interface dipole originating from a thin negative charged reaction layer formed between the AlTa alloy and dielectric layer. In order to further increase the stability of the AlTa alloy while still obtaining φm tuning, N was added to make AlTaN. These alloy electrodes resulted in effective work function values of ~5.13 eV after a 1000°C anneal making them suitable candidates for PMOS electrodes. Chapter 6 shows a new method that can tune the effective work function utilizing dipole layers has been demonstrated. Continued work function values can be expected by modifying the dipole strengths. This routine can potentially provide a new method for the metal gate work function research for the future wide gape semiconductor device.
Nonlinear Behavioral Modeling of Quadrature Modulators and Analysis of Impacts on Wireless Communication Systems
(2008-08-29) Li, Minsheng; Kevin G. Gard, Committee Chair; Mark Johnson, Committee Member; Michael B. Steer, Committee Member; Huaiyu Dai, Committee Member
Rare-Earth Doped Wide Bandgap Oxide Semiconductor Materials and Devices
(2009-09-16) Wellenius, Ian Patrick; Mark Johnson, Committee Member; Leda Lunardi, Committee Member; Robert Kolbas, Committee Member; Henry O. Everitt, Committee Member; John F. Muth, Committee Chair
Simulation Methodology to Compare Emerging Technologies for Alternatives to Silicon Gigascale Logic Device
(2007-09-22) Jin, Yawei; Mark Johnson, Committee Member; W. Rhett Davis, Committee Member; Doug Barlage, Committee Chair; Veena Misra, Committee Member
Stimulated Emission and Laser Action from Gallium Nitride, Aluminium Gallium Nitride, Aluminium Gallium Nitride⁄Gallium NitrideQuantum Wells and Heterostructures
(2007-11-06) Al-Ajmi, Fahed Shammakh; Veena Misra, Committee Member; Mark Johnson, Committee Member; Doug Barlage, Committee Member; John Muth, Committee Member; Robert Kolbas, Committee Chair
Stimulated emission and laser action at 77K and room temperature from GaN and AlGaN epilayers grown by metal-organic vapor chemical deposition on silicon substrates are presented. Electron-hole plasma is found to be the responsible for stimulated emission in these material at room temperature and 77K. Laser action with well developed Fabry-Perot modes from multiple bands was achieved at both temperatures from the GaN epilayer, A value of 2.9 is obtained for the effective index of refraction at room temperature. Also, stimulated emission from AlGaN⁄GaN single quantum wells and heterostructures is demonstrated at 77K and room temperature. Multiple bands exhibiting laser action are demonstrated from a 7.2 nm thick Al(0.06)Ga(0.94)N⁄GaN single quantum well at 77K and room temperature, and an effective index of refraction of 2.70 is obtained at room temperature. The shortest wavelength for laser action from an Al(0.13)Ga(0.87)NବGaN heterostructures at room temperature is also presented. Phonon-assisted stimulated emission from AlGaN⁄GaN quantum wells is first observed in this work. Laser action at 1LO down from multiple bands is demonstrated. Phonon sideband laser action is also observed without any near band edge stimulated emission at 77K.
Study of Mn Doped GaN for Spintronic Applications
(2006-11-20) Arkun, Fevzi Erdem; Gerd Duscher, Committee Member; Nadia El-Masry, Committee Chair; Salah Bedair, Committee Co-Chair; Mark Johnson, Committee Member
Spintronics is an emerging field in which the spin of carriers in addition to the charge of carriers can be used to achieve new functionalities in electronic devices. The availability of materials exhibiting ferromagnetism above room temperature is prerequisite for realizing such devices. Materials suitable for spintronic applications are desired to be compatible with conventional growth and fabrication techniques in addition to exhibiting above room temperature ferromagnetic properties. In this research the growth of GaMnN has been achieved on (0001) sapphire substrates by metal organic chemical vapor deposition using TMGa and (EtCp₂)Mn as organometallic precursors. Magnetic characterization of the grown films was performed by a Superconducting Quantum Interference Device (SQUID) at room temperature. Ferromagnetic properties were observed above room temperature for this material. Co-doping of ferromagnetic GaMnN by silicon and magnesium was performed and ferromagnetic properties of GaMnN have been found to depend on the Fermi level in the crystal itself. The mechanism of ferromagnetism in this material was proposed to be carrier mediated. The magnetic properties were also altered by carrier transfer at a heterointerface indicating that the electronic band structure of the crystal affects the magnetic properties of this material. Growth of GaN based blue light emitting diode structures were achieved by MOCVD using conventional organometallic sources. Fabrication of grown structures was performed in a clean room using standard fabrication techniques for III-Nitrides. Two spin-LEDs containing GaMnN injector layers were also grown to determine the polarization state of the emission from these spin-LEDs.