Browsing by Author "Paul Franzon, Committee Member"

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Current-Mode Band-Limited Signaling for Global On-chip Interconnects
(2004-03-02) Bashirullah, Rizwan; Wentai Liu, Committee Chair; Ralph Cavin, Committee Member; Paul Franzon, Committee Member; Gianluca Lazzi, Committee Member
Global on-chip interconnects are a limiting factor in modern high performance VLSI systems due to cross-talk noise, signal delay and wire bandwidth constraints. This dissertation addresses these limitations with a fundamental change in signaling technique — the use of current-mode band-limited pulses. This work is intended to establish the theoretical basis for the proposed signaling scheme while formulating its impact on signal delay, bandwidth and cross-talk noise both analytically and experimentally. Simple yet accurate closed-form delay and power dissipation expressions for inverter driven on-chip interconnects with arbitrary receive-end termination are presented. The solutions can be used for both resistive and capacitive termination to adequately model current and voltage mode sensing used in repeaters for interconnect signaling schemes. The performance of band-limited pulse signaling for cross-talk noise reduction in high-density on-chip interconnects is addressed using reduced edge-rate pulses. A comparative analysis is presented to evaluate performance in cross-talk noise, driver/receiver power dissipation and propagation delay. Test chips fabricated in AMI 1.6μm bulk CMOS technology are used to experimentally evaluate the performance of the proposed techniques. This dissertation also explores a novel on-chip adaptive bandwidth bus (ABB) designed to automatically increase or decrease the interconnection bandwidth to track the input data activity envelope, thereby minimizing the static power dissipation associated with low impedance current sensing without a penalty in maximum attainable data rate. To demonstrate the feasibility of the proposed bus, 'analog' and 'digital' implementations are fabricated in AMI 1.6μm and TSMC 0.35μm CMOS technologies, respectively. In addition, a power dissipation modeling approach based on circuit-level and statistical analysis of microprocessor data streams is presented to evaluate the performance of the proposed bus. Attaining a maximum aggregate bandwidth of 16Gb/s (i.e. 1Gb/s per line) across lossy on-chip interconnects spanning 1.75cm in length, the digital bus core dissipates approximately 93mW with a supply of 2.5V and signal activity of 0.5. Experimental results indicate a reduction in power of 50% over current-mode (CM) sensing, and an improvement in interconnection delay and signaling bandwidth of 35%-70% and 66% over voltage-mode (VM) sensing, respectively.
Dynamic Electrothermal Simulation using Compact Macromodel of Standard Cells.
(2010-10-11) Priyadarshi, Shivam; Michael Steer, Committee Chair; David Schurig, Committee Member; Paul Franzon, Committee Member
Efficient Implementation of MIMO Detectors for Emerging Wireless Communication Standards.
(2010-08-30) Moezzi Madani, Nariman; William Davis, Committee Chair; Paul Franzon, Committee Member; Huaiyu Dai, Committee Member; Richard Warr, Committee Member; Brian Floyd, Committee Member
Ingress Rate Control in Resilient Packet Rings
(2005-10-19) Thombare, Asavari; Michael Devetsikiotis, Committee Member; Paul Franzon, Committee Member; Ioannis Viniotis, Committee Chair
Resilient Packet Ring (RPR) Protocol is becoming popular in Metro Networks due to its rich features. One of these features is the Fairness and Flow Control mechanism. RPR is standardized as IEEE 802.17 and claims that there will be no frame loss inside the network under normal operation. This is achieved through feedback flow control messages. Traffic rate is controlled at the ingress itself based on these messages. We concentrate on the Ingress Rate Control scheme where the local station adds traffic to the ringlet based on the allocated rate limits and FAIR rate limits to achieve fairness in the ring network. The research presented in the thesis tries to achieve three different goals. We implement the Rate Control scheme in software to identify early implementation level issues and then implement it in hardware. We achieve a speed of 10 Gbps with our hardware implementation. We also achieve a full throughput at minimum frame size of 24 bytes. The hardware implementation is tested for compliance with the standard IEEE 802.17. In the simulation study part of the research, we observe the response of individual shapers under compliance testing. We concentrate on the feature of bandwidth reclamation in detail and show that the standard implementation is able to provide bandwidth reclamation under different scenarios. We also study the effect of alternative methods for implementation of Fairness Eligible Shaper. The implementation and simulation parts of the thesis concentrate on the Single Transit Queue Implementation. In the third part we perform analysis of the buffer size requirement under worst case conditions in Dual Transit Queue Architecture. We compare our analysis with the standard and identify various components which affect the buffer size. The buffer size is chosen such that there will be no frame loss due to overflow of the Secondary Transit Queue.
Lead Zirconate Titanate (PZT) Based Thin Film Capacitors For Embedded Passive Applications
(2003-08-21) Kim, Taeyun; Robert Croswell, Committee Member; Paul Franzon, Committee Member; Jon-Paul Maria, Committee Chair; Gerd Duscher, Committee Member; Angus Kingon, Committee Chair
Investigations on the key processing parameters and properties relationship for lead zirconate titanate (PZT, 52/48) based thin film capacitors for embedded passive capacitor application were performed using electroless Ni coated Cu foils as substrates. Undoped and Ca-doped PZT (52/48) thin film capacitors were prepared on electroless Ni coated Cu foil by chemical solution deposition. The effects of processing parameters on the phase evolution, microstructures, dielectric properties, and reliability were investigated. Electroless Ni coated Cu foil was selected as substrate for its low cost, oxidation resistance and lamination capability. When annealed at 450 °C, electroless Ni coated Cu foil showed transformation from amorphous Ni to crystalline phase of Ni-P (mostly Ni₃P) and Ni metal. For PZT (52/48) thin film capacitors on electroless Ni coated Cu foil, voltage independent (zero tunability) capacitance behavior was observed. Dielectric constant reduced to more than half of the identical capacitor processed on Pt/SiO₂/Si. Dielectric properties of the capacitors were mostly dependent on the crystallization temperature. Capacitance densities of almost 350 nF/cm² and 0.02-0.03 of loss tangent were routinely measured for capacitors crystallized at 575-600 °C. Leakage current showed dependence on film thickness and crystallization temperature. It is speculated that space charge limited conduction (SCLC) seems to be consistent with conduction mechanism in PZT thin films on electroless Ni. From a two-capacitor model, the existence of a low permittivity interface layer (permittivity -30) was suggested. Also it is suggested a high concentration of traps exist inside the PZT capacitor. Interface reaction between PZT thin film and electroless Ni was suggested to be responsible for measured electrical properties. The interfacial layer might be composed of unreacted oxide, phosphate, and phosphides possibly from phosphorous diffused from electroless Ni into PZT bulk. For Ca-doped PZT (52/48) thin film capacitors prepared on Pt, typical ferroelectric and dielectric properties were measured up to 5 mol%Ca doping. Further addition up to 10 mol % changed the lattice parameter of the unit cell, and reduced dielectric properties were observed. The possibility of Ca acceptor doping is suggested. When Ca-doped PZT (52/48) thin film capacitors were prepared on electroless Ni coated Cu foil, phase stability was influenced by Ca doping and phosphorous content. Dielectric properties showed dependence on the crystallization temperature and phosphorous content. Capacitance density of -400 nF/cm² was achieved, which is an improvement by more than 30% compared to undoped composition. Ca doping also reduced the temperature coefficient of capacitance (TCC) less than 10%, all of them were consistent in satisfying the requirements of embedded passive capacitor. Leakage current density was not affected significantly by doping. Interface control by controlled pO² crystallization was found to be not effective in interface layer mitigation. Phase purity, dielectric properties, surface microstructure, and pO² were found to have a correlated dependence. To tailor the dielectric and reliability properties, ZrO² was selected as buffer layer between PZT and electroless Ni. Only RF magnetron sputtering process could yield stable ZrO² layers on electroless Ni coated Cu foil. Other processes resulted in secondary phase formation, which supports the reaction between PZT capacitor and electroless Ni might be dominated by phosphorous component. Incorporation of ZrO² layers reduced maximum capacitance density by 10 %(- 350 nF/cm²) due to lower permittivity of ZrO² layer. Significantly improved leakage current densities were measured for PZT thin film capacitors on ZrO₂. For PZT thin film capacitors incorporating 100 nm thick ZrO₂ layer, leakage current density of 10⁻⁸ A/cm² was measured at 25 VDC, which is more than three orders of magnitude lower than those directly deposited on electroless Ni coated Cu foil. The complete set of experimental data provides validation and process conditions for the use of PZT thin films on low cost electroless Ni coated Cu foil substrate as embedded capacitors in high density printed circuit boards.
A Multi-Channel Wireless Implantable Neural Recording System
(2009-04-27) Yin, Ming; Paul Franzon, Committee Member; Gianluca Lazzi, Committee Co-Chair; Maysam Ghovanloo, Committee Co-Chair; Kevin Gard, Committee Member; Xiaoyong Zheng, Committee Member; Donald Woodward, Committee Member
ABSTRACT YIN, MING. A Multi-Channel Wireless Implantable Neural Recording System. (Under the direction of Dr. Maysam Ghovanloo). This dissertation presents a multi-channel implantable wireless neural recording (WINeR) system for electrophysiology and behavioral neuroscience research applications. This system consists of two units: a system-on-a-chip (SoC) transmitter unit and a receiver unit built with off-the-shelf components. A novelty of the WINeR system is in its utilization of a wireless single-slope ADC technique by inserting a wireless link in between a pulse width modulator and a time-to-digital converter (TDC). This technique not only offers the WINeR system the benefit of a single-slope ADC, but also makes the WINeR transmitter unit very simple, low power, and small in regards to chip area. In addition, by directly transmitting pulse width modulation (PWM) signal, the pulse rate over the wireless link is reduced to the sampling rate, while a moderate system resolution can still be achieved. Another novelty of this system is that its transmitter uses an asynchronous (clockless) topology and achieves very low noise levels by eliminating the on-chip clock. Some of the other features of this system are the wideband FSK demodulator and FPGA-based TDC in the receiver unit capable of achieving high resolution, low noise, low power, low cost, and ease of implementation. A 32-channel WINeR transmitter prototype is implemented in a standard CMOS technology, and operates in the 900MHz ISM band. A prototype WINeR receiver is also built using off-the-shelf components with up to 75MHz bandwidth. A custom developed VC++ GUI running on a PC interface with the receiver unit through a USB port and facilitates data storage and visualization. In addition, detailed noise analysis is conducted both theoretically and experimentally to further characterize the performance of the system. Finally, the full functionality of the entire WINeR system has been validated from bench-top, and through in vivo experiments on rats.
Multifunction Periodic Switching Front-End Circuits for Multi-Antenna Integrated Wireless Receivers
(2009-12-04) Krishnamurthy, Gautham; Kevin Gard, Committee Chair; Paul Franzon, Committee Member; Antonio Montalvo, Committee Member; Harvey Charlton, Committee Member
In the domain of integrated wireless receivers, multi-antenna techniques are gaining increasing relevance and application as a result of the many advantages they offer. Chief among these advantages are improved throughput by spatial multiplexing in MIMO systems, higher SNR by diversity gains and directional gain / interference cancellation by phased array combining. However, the current state-of-the-art in multi-antenna receivers is to resort to the duplication of front-ends for each separate antenna. This leads to the obvious drawback of higher system area, power and cost. This research addresses these drawbacks of the traditional approach with a new receiver architecture termed the Switched Front-end Multi-antenna Receiver (SFMR) architecture. The SFMR style employs fast periodic switching within the front-end in order to permit the sharing of as much of the downstream circuitry following the antenna as possible. Two types of periodic switching are primarily investigated: Time-Division Multiplexing (TDM) to exploit spatial multiplexing gains and Coherent Combining (CC) for SNR improvement like in beamforming and diversity systems. A solution is proposed to address the cross-interference between multiplex channels that affected previous attempts at TDM for multiple receive antennas. The theoretical framework from first principles for the analysis and design of these periodic switching systems from a radio hardware viewpoint is developed. Closed form relations for noise figure are developed that are useful for quick figure of merit evaluations of the SFMR architecture. Four front-ends based on the SFMR architecture are implemented as CMOS designs in 0.18 ÃŽÂ¼m technology for 2.4 GHz RF signals to validate the theory. Two designs are single-ended versions of a quad-amplifier array, while one is a differential version of the same. The final design is a dual-antenna differential direct-conversion receiver including all circuit blocks down to the baseband demultiplexing. The differential front-ends are multifunctional in the sense that the circuits may be reconfigured digitally and, with the help of a programmable high-speed digital controller, put in either TDM or CC modes of operation. All these designs are characterized fully to determine their gain, matching, noise and linearity performance, as also their time-domain operation. Thus, an understanding of the challenges and rewards posed by the SFMR architecture is obtained.
Optimal Design of Vibration-based Energy Harvesting Systems using Magnetostrictive Material (MsM).
(2010-09-10) Hu, Jingzhen; Alex Huang, Committee Chair; Fuh-Gwo Yuan, Committee Chair; Paul Franzon, Committee Member; Veena Misra, Committee Member
A Testbed for Technology Characterization
(2009-12-08) Iles, Philip Michael; W. Rhett Davis, Committee Chair; Paul Franzon, Committee Member; Xun Liu, Committee Member
As feature sizes continue to decrease, fundamental properties of MOSFET devices begin to hinder the performance gains from one generation to another. The advent of the Tunneling Field Effect Transistor (TFET) provides hope for continued reduction in feature size whilst solving some of the scaling issues such as leakage current. The purpose of this work is to discuss key metrics that help to quantify the improvements among technology nodes, specifically a comparison between TFETs and traditional MOSFETs. Test structures that allow for the measurement of on and off current, device speed, variation as it relates to on current and threshold voltage, as well as SRAM yield and bitcell read and write noise margins are discussed. In addition, a slight modification to a rapid characterization test structure used to measure threshold variation is proven to help reduce leakage seen within the test structure. Lastly, the structures are actually fabricated in a 90nm bulk and a 45nm SOI process and measurements from the 90nm bulk process are presented.
Transistor Modeling using Advanced Circuit Simulator Technology
(2002-04-30) Kriplani, Nikhil M; Michael Steer, Committee Chair; Paul Franzon, Committee Member; Griff Bilbro, Committee Member
The advanced MOSFET model based on the Berkeley Short Channel IGFET Model (BSIM) version 4 is implemented in the circuit simulator Transim. The model is implemented as a charge controlled model using object-oriented programming and automatic differentiation. The result is a dramatically simplified approach to implementing the BSIM4 model in a simulator. The modeling technique does not use the associated discrete modeling approach commonly used in circuit simulators with the result that off-the-shelf numerical solvers can be used. The model is a simulator independent model and the same model code can be used for DC, transient and harmonic balance analysis. Implementation of the model was completed in 7 months with 17 pages of C++ code compared to the original code for the model implemented in SPICE that was 200 pages long. Results for an NMOS circuit are presented for DC and transient analysis.