Browsing by Author "Rhett Davis, Committee Member"

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Analysis and Design Considerations for AC Coupled Interconnection Systems
(2005-03-29) Mick, Stephen; Paul D. Franzon, Committee Chair; John Muth, Committee Member; Rhett Davis, Committee Member; Jacqueline Krim, Committee Member
As the process technologies for microelectronic integrated circuits continue to improve, both the amount of integrated, on-chip functionality and the number of required off-chip interconnections (I/O) will continue to increase. These I/O will not only become more numerous but also will need to be packed densely and be capable of operating both with high bandwidth and low power. Packaging technology research is aimed at increasing I/O density and circuit research is underway to improve the bandwidth and power performance of I/Os. Advances are being made in each of these areas, but industrial roadmaps predict that these advances will not keep pace with the needed improvements. The research in this dissertation addresses this widening technological gap. The central thesis in this work hinges on the recognition that arrays of densely packed, low-power, high-bandwidth I/Os can be created if the physical structure of each I/O is optimized for the type of information it must transmit. For example, the DC component of digital signals carries no information. Instead, digital signals contain information at frequencies well above DC (where the exact frequency spectrum of the information depends upon the edge rate of the data transitions). This can be exploited by recognizing that AC information can be transmitted across a boundary with non-contacting structures such as two plates of a capacitor or two coupled inductors. An I/O array can then be built with non-contacting structures for AC signals and direct contacts such as solder bumps only where DC signal transfers are needed. In this way, AC signal paths are freed from the mechanical constraints of direct, contacting structures and both the compliance and rework problems encountered in other high density interconnect technologies can be alleviated. Capacitive and Inductive AC Coupled Interconnections are extensively analyzed and measured in this work and presented as a means to provide an array of sub-100 micrometer pitched, low-power, multi-gigabit per second per pin interconnections. A packaging structure that enables AC Coupled Interconnections is also presented.
Behavioral Modeling and Characterization of Nonlinear Operation in RF and Microwave Systems
(2006-06-13) Walker, Aaron; Rhett Davis, Committee Member; Gianluca Lazzi, Committee Member; Michael Steer, Committee Chair; Kevin Gard, Committee Member
Modeling and characterization strategies were developed to capture the complex nonlinear behavior of both the components within an RF circuit and within an assembled system. Metrology techniques using common laboratory instrumentation were developed for the remote characterization of assembled RF devices and the result of this characterization is presented here for the first time. In addition, two novel intermodulation relative phase measurement systems were developed that have 90 dB of dynamic range which is a considerable improvement over existing systems. This enables the measurement of weaker nonlinearities and increases the accuracy of these measurements. A behavioral modeling architecture and extraction procedure were developed to take advantage of the metrology techniques to allow the separation of odd-ordered nonlinear effects and baseband upconversion effects in several amplifiers. The results of applying this modeling strategy has produced a general model capable of predicting both magnitude and phase asymmetries in nonlinear components for the first time. Concepts from the remote characterization, intermodulation phase measurement systems, and the modeling efforts were combined to demonstrate the extraction of two-port transmission parameters from one-port measurements in a archetypal circuit of an integrated bandpass filter in an RF front-end. It is shown how this information can be used to tune a filter.
Class-E Power Amplifier Design and Back-Telemetry Communication for Retinal Prosthesis
(2004-01-24) Pundi, Bharatram Satyanarayanan; Wentai Liu, Committee Chair; Rhett Davis, Committee Member; Gianluca Lazzi, Committee Member
This thesis discusses the power link in the retinal prosthesis project that aims to provide vision to the profoundly blind. Clinical experiments have confirmed that electrical stimulation can be used to duplicate the action of photoreceptors in the retina to provide vision to blind patients suffering from RP/AMD. The retinal prosthesis system consists of an intraocular unit implanted inside the eye and a separate extraocular unit. The micro-stimulator involved in retinal prosthesis consists of multiple electrodes arranged in two-dimensional array and is a part of the intraocular unit. The micro-stimulator needs data and power to be transferred wirelessly from the extraocular unit. The power link consists of a highly efficient Class-E driver that transfers power inductively to the intraocular unit. A Class-E power driver is developed to suit the requirements and has been analyzed. The effect of the loaded Q variations on the Class-E circuit has been studied. Back-telemetry from the intraocular unit is necessary and is achieved through load modulation in the intraocular unit. A novel variation of PWM encoding has been conceived and employed to combine data and clock. The data detection unit consisting of an envelope detector and a PWM decoder has been developed. The data received is processed in the extraocular unit to adjust the power transfer and achieve power regulation. The format for data transmission has been proposed to arrange data into continuous packets, which includes error detection capabilities.
Design, Analysis and Realtime Realization of Artificial Neural Network for Control and Classification
(2006-05-11) Dong, Puxuan; Rhett Davis, Committee Member; Wesley Snyder, Committee Member; Mohan Putcha, Committee Member; Griff L. Bilbro, Committee Chair; Mo-Yuen Chow, Committee Member
Artificial neural networks (ANNs) are parallel architectures for processing information even though they are usually realized on general-purpose digital computers. This research has been focused on the design, analysis and real-time realization of artificial neural networks using programmable analog hardware for control and classification. We have investigated field programmable analog arrays (FPAAs) for realizing artificial neural networks (ANN). Our research results and products include a general theoretical limit on the number of neurons required by an ANN to classify a given number of data points, a design methodology for the efficient use of specific FPAA resources in ANN applications, several multi-chip FPAA implementations of ANNs for classification experiments, several single-chip FPAA implementations of analog PID controllers for an unmanned ground vehicle (UGV), experimental evaluation of FPAA PID controllers with a conventional digital PID controller on a UGV, and finally a single-chip FPAA implementation of a (non-linear) ANN controller for comparison with the previous FPAA PID controller on a UGV. 2 These results are collected as four papers formatted for publication and comprising chapters 3, 4, 5, and 6 of this thesis. The first paper develops our general bound for neural network complexity. The second presents a systematic approach based on the upper bound theory for implementing and simplifying neural network structures in FPAA technology. In the third paper, a FPAA based PID controller was designed and characterized in a path-tracking UGV; some of the results from this report are used as a baseline in the fourth paper. In the fourth paper, a FPAA based ANN controller is designed to control a path-tracking UGV and is investigated analytically and with simulation before its performance was experimentally compared to the previously designed FPAA PID controller regarding speed, stability and robustness. In conclusion, this dissertation focuses on the design, analysis and real-time realization of artificial neural networks. The proposed upper bound for neural network complexity provides guidelines for reducing hardware requirements and applies to any layered ANN approach to classification. It is complemented by the neural network structure simplification method which exploits specific features available in the FPAA technology which we used in our experiments and which we believe possess great potential for future real-time control and classification applications.
Flip Chip testing with a capacitive coupled probe chip.
(2003-03-12) Stanaski, Andrew; Dennis Bahler, Committee Member; Rhett Davis, Committee Member; Wentai Liu, Committee Member; Paul Franzon, Committee Chair
Testing integrated circuits that employ an area array of I/O presents unique challenges because the face of the chip is not visible for probing. On chips that use perimeter bond pads the face of the chip is exposed, so signals on the wiring in the top layer metal may be probed while the chip is in operation. This is not possible when the face of the chip is hidden. This work proposes a way to probe test points on the top layer metal of chips that use area I/O. The method works by attaching the chip to a specially designed probe chip instead of the normal packaging. Metal pads on the top layer of the probe chip correspond to lines on the top layer of the chip being tested. These points form a capacitive coupling between the chips, letting the probe chip read the signals at the test points. This leaves the original chip largely unchanged, and allows critical signals to be probed. The geometry of the test points is examined and evaluated using a field solver for their potential to couple between the chips. A square section of metal roughly 6 mm on a side provides 1 fF coupling capacitance, enough for a receiver on the probe to reproduce the signal. The work continues with the design of a receiver circuit to amplify the small input from the test points. The receiver employs a differential amplifier followed by an inverter to amplify the signal without excessive loading at the input. Simulations of the receiver demonstrate its ability to recreate the signal. Additional simulations measure the performance of the receiver under varying conditions, and explore the operational characteristics. This work also describes the design of a four issue superscalar microprocessor that was used as a reference for explorations of systems design for multichip modules (MCMs). This work focused on the chip testing aspect of area array I/O chips used in an MCM. Other work investigated partitioning, routing, and other system design issues. Finally, the work gives an outline of the CAD tool setup created for use at N. C. State University. The design kit created supports research as a vehicle for creating chips, and for integrating research CAD algorithms.
Implementation of Double Precision Floating Point Arithmetic
(2007-03-08) Sudarsanam, Yasaswini; Xun Liu, Committee Member; Rhett Davis, Committee Member; Paul Franzon, Committee Chair
Floating Point Arithmetic is extensively used in the field of medical imaging, biometrics, motion capture and audio applications, including broadcast, conferencing, musical instruments and professional audio. Many of these applications need to solve sparse linear systems that use fair amounts of matrix multiplication. The objective of this thesis is to implement double precision floating point cores for addition and multiplication .These cores are targeted for Field Programmable Gate Arrays because FPGAs give the designer good control over the number of I/O pins and utilization of on chip memory. FPGAs are also comparable to floating point processors in their power consumption. The multiplier and adder cores conform to the IEEE 754 standard for double precision. The design is implemented on Xilinx ISE 8.2i and has been simulated on ModelSim 6.1i.The thesis pays significant attention to the analysis of the adder and multiplier cores in terms of pipelining and area so as to maximize throughput in any manner possible. It further throws light on variations of power with pipelining. Power measurements are done using XPower provided by ISE.
Intracellular recording with low-power low-noise CMOS voltage and current clamp circuits
(2007-11-18) Silva, Pradeep Charles; Kevin Gard, Committee Chair; Rhett Davis, Committee Member; Douglas Barlage, Committee Member
Low Power Interconnect Circuits using Silicon Carriers
(2009-05-07) Gadfort, Peter; Paul Franzon, Committee Chair; Michael Steer, Committee Member; Rhett Davis, Committee Member
Due to the ever-increasing complexity of the tasks that modern electronic devices are expected to carry out, many devices incorporate multiple chips linked via input/output pins and transmission lines on a single board in multi-chip modules. The interconnects between these chips are a large source of power drain due to the parasitic capacitance loading of the input/output pads on the chip and the transmission lines.
By moving multiple chips onto the same substrate to form a "virtual" chip, the I/O pins and transmission lines used to connect the chips can be replaced with a silicon carrier and micro-bumps. By creating these "virtual" chips, incompatible technologies such as GaAs and silicon substrate can be merged into a single package. Using silicon carriers also allows for the use of fine-pitch interconnects down to 2 ÃŽÂ¼m - built into the silicon carrier - which is a large improvement over current organic or ceramic packaging technologies.
This work investigates a current mode circuit proposed by Zhang to achieve a significant power advantage over current signaling techniques and packaging technologies. This will be achieved by utilizing silicon carrier technology for the interconnects between integrated circuits. The interconnects can span the carrier from a few millimeters up to several centimeters depending the on the interconnect structure. By trading the bandwidth of the silicon carrier for length of the interconnect, various lengths can be chosen for the desired data throughput. Also, by trading noise margin for reduced power in the I/O circuits a significant power reduction in the circuits can be achieved.
This work will show that a power reduction of 75%, for the power metric of power per gigabit per second, is possible over current organic packaging technologies and a standard driver, by using the improved driver and the silicon carrier interconnects. These circuits were designed in a predictive 45 nm process and the achieved bit error rates were on the order of 10^-15 errors/bit while operating at 4 Gbps.
Modelling Colored Noise under Large-Signal Conditions
(2006-01-05) Kriplani, Nikhil M; Griff Bilbro, Committee Member; Doug Barlage, Committee Member; Rhett Davis, Committee Member; Michael B. Steer, Committee Chair
A time-domain simulation approach to modelling colored noise in electrical circuits is described. This approach tries to place minimal restrictions on the magnitude and the nature of the noise present in a circuit in an effort to capture the effects of nonlinear interactions between signal and noise. The approach uses the mathematical theory of nonlinear dynamics and chaos to produce stochastic-looking series using simple deterministic iterative rules or maps. The characteristics of these series can be modified easily to produce a large range of spectral characteristics. The advantage of using the chaotic maps approach is that modifying the spectral characteristics usually requires the tweaking of a small number of parameters. This is in contrast to more traditional time-series-based approaches to noise generation which require a large number of parameters to accurately model the characteristics of common sources of noise found in electrical circuits. The validity of this approach to modelling is tested by implementing a unified deterministic and stochastic framework of equations in a high dynamic range simulator. The resulting stochastic system of equations describing a nonlinear noisy network are setup and solved assuming the Stratonovich interpretation. Simulated results are compared with measured results using two representative circuits. The first circuit is a varactor-tuned voltage-controlled oscillator and simulated phase noise at the output of the circuit is compared with measured values. The second circuit is a low-noise X-band MMIC power amplifier and the effect of noise on the amplification of this device is investigated. Gain versus input power curves are generated in simulation when the circuit is fed with large levels of input noise and contrasted with measurement. Both these cases demonstrate that this approach to the modelling of large levels of noise is valid and perhaps even essential in order to accurately predict the effects of having non-negligible levels of noise in an electronic circuit.