Browsing by Author "S. Purushothaman Iyer, Committee Member"

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Length Adaptive Processors: A Solution for the Energy/Performance Dilemma in Embedded Systems
(2009-04-22) Iyer, Balaji Viswanathan; Eric Rotenberg, Committee Member; Dr. Thomas M. Conte, Committee Chair; W. Rhett Davis, Committee Member; S. Purushothaman Iyer, Committee Member
Embedded-handheld devices are the predominant computing platform today. These devices are required to perform complex tasks yet run on batteries. Some architects use ASIC to combat this energy-performance dilemma. Even though they are efficient in solving this problem, an ASIC can cause code-compatibility problems for the future generations. Thus, it is necessary for a general purpose solution. Furthermore, no single processor configuration provides the best energy-performance solution over a diverse set of applications or even throughout the life of a single application. As a result, the processor needs to be adaptable to the specific workload behavior. Code-generation and code-compatibility are the biggest challenges in such adaptable processors. At the same time, embedded systems have fixed energy source such as a 1-Volt battery. Thus, the energy consumption of these devices must be predicted with utmost accuracy. A gross miscalculation can cause the system to be cumbersome for the user. In this work, we provide a new paradigm of embedded processors called Dynamic Length-Adaptive Processors that have the flexibility of a general purpose processor with the specialization of an ASIC. We create such a processor called Clustered Length-Adaptive Word Processor (CLAW) that is able to dynamically modify its issue width with one VLIW instruction overhead. This processor is designed in Verilog, synthesized, DRC-checked, and placed and routed. Its energy and performance values are reported using industrial-strength transistor-level analysis tools to dispel several myths that were thought to be dominating factors in embedded systems. To compile benchmarks for the CLAW processor, we provide the necessary software tools that help produce optimized code for performance improvement and energy reduction, and discuss some of the code-generation procedures and challenges. Second, we try and understand the code-generator patterns of the compiler by sampling a representative application and design an ISA opcode-configuration that helps minimize the energy necessary to decode the instructions with no performance-loss. We discover that having a well designed opcode-configuration, not only reduces energy in the decoder by also other units such as the fetch and exception units. Moreover, the sizable amount of energy reduction can be achieved in a diverse set of applications. Next, we try to reduce the energy consumption and power-dissipation of register-read and register-writes by using popular common-value register-sharing techniques that are used to enhance performance. We provide a power-model for these structures based on the value localities of the application. Finally, we perform a case-study using the IEEE 802.11n PHY Transmitter and Decoder and identify its energy-hungry units. Then, we apply our techniques and show that CLAW is a solution for such hybrid complex algorithms for providing high-performance while reducing the total energy.
Mechanisms for Protecting Software Integrity in Networked Systems
(2008-12-02) Kil, Chongkyung; Tao Xie, Committee Member; Peng Ning, Committee Chair; Douglas S. Reeves, Committee Member; S. Purushothaman Iyer, Committee Member
Protecting software integrity is a key to successfully maintain its own credibility and reduce the financial and technical risks caused from a lack of integrity. Although researchers have been putting effort on improving software development techniques and preventing human errors during the software development process, it is still a daunting task to make non-vulnerable software in practice. For example, the national vulnerability database shows that a set of new software vulnerabilities are discovered every day. Since developing non-vulnerable software is hardly achievable, in this research, we look for a way to achieve software integrity while they are used. In particular, this dissertation investigates three mechanisms to protect software integrity at runtime. Firstly, this dissertation presents a protection mechanism that can thwart attacks that try to exploit memory corruption vulnerabilities of software. The protection mechanism is provided by randomizing the program's runtime memory address layout and the memory objects. As a result, it hinders memory corruption attacks by preventing an attacker being able to easily predict their target addresses. The protection mechanism is implemented by a novel binary rewriting tool that can randomly place the code and data segments of programs and perform fine-grained permutation of function bodies in the code segment as well as global variables in the data segment. Our evaluation results show minimal performance overhead with orders of magnitude improvement in randomness. Secondly, this dissertation investigates a vulnerability identification mechanism named as CBones that can discover how unknown vulnerabilities in C programs are exploited by verifying program structural constraints. This mechanism is also useful in developing integrity patches for vulnerable programs where applying security patch is increasingly common in these days. CBones automatically extracts a set of program structural constraints via binary analysis of the compiled program executable. CBone then verifies these constraints while it monitors the program execution to detect and isolate the security bugs. Our evaluation with real-world applications that known to have vulnerabilities shows that CBones can discover all integrity vulnerabilities with no false alarms, pinpoint the corrupting instructions, and provide information to facilitate the understanding of how an attack exploits a security bug. Lastly, this dissertation identifies the need of dynamic attestation to overcome the limitations of existing remote attestation approaches. To the best of our knowledge, we are the first to introduce the notion of dynamic attestation and propose use of dynamic system properties to provide the integrity proof of a running system. To validate our idea, we develop an application-level dynamic attestation system named as ReDAS(Remote Dynamic Attestation System) that can verify runtime integrity of software. ReDAS provides the integrity evidence of runtime applications by checking their dynamic properties: structural integrity and global data integrity. These properties are collected from each application, representing the application's unique runtime behavior that must be satisfied at runtime. ReDAS also uses hardware support provided by TPM to protect the integrity evidence from potential attacks. Our evaluation with real-world applications shows that ReDAS is effective in capturing runtime integrity violations with zero false alarms, and demonstrates that ReDAS incurs 8% overhead on average while performing integrity measurements.
Mitigating Voice over IP Spam Using Computational Puzzles
(2008-08-31) Zhou, Yuzheng; S. Purushothaman Iyer, Committee Member; Peng Ning, Committee Chair; Ting Yu, Committee Member
Polymorphic and Metamorphic Malware Detection
(2009-05-16) Zhang, Qinghua; S. Purushothaman Iyer, Committee Member; Peng Ning, Committee Member; Wenye Wang, Committee Member; Douglas S. Reeves, Committee Chair
Software attacks are a serious problem. Conventional anti-malware software expects malicious software, malware, to contain fixed and known code. Malware writers have devised methods of concealing or constantly changing their attacks to evade anti-malware software. Two important recent techniques are polymorphism, which makes uses of code encryption, and metamorphism, which uses a variety of code obfuscation techniques. This dissertation presents three new techniques for detection of these malware. The first technique is to recognize polymorphic malware that are encrypted and that self-decrypt before launching the attacks in network traffic. We propose a new approach that combines static analysis and instruction emulation techniques to more accurately identify the starting location and instructions of the decryption routine, which is characteristic of such malware, even if self-modifying code is used. This method has been implemented and tested on current polymorphic exploits, including ones generated by state-of-the-art polymorphic engines. All exploits have been detected (i.e., a 100% detection rate), including those for which the decryption routine is dynamically coded or self-modifying. The method has also been tested on benign network traffic and Windows executables. The false positive rates are approximately .0002% and .01% for these two categories, respectively. Running time is approximately linear in the size of the network payload being analyzed and is between 1 and 2 MB/s. The second technique is a means of recognizing metamorphic malware which has a transformed program image with equivalent or updated functionalities. We propose a new approach that uses fully automated static analysis of executables to summarize and compare program semantics, based primarily on the pattern of library or system functions which are called. This method has been prototyped and evaluated using randomized benchmark programs, instances of known malware program variants, and utility software available in multiple releases. The results demonstrate three important capabilities of the proposed method: (a) it does well at identifying metamorphic variants of common malware. (b) it distinguishes easily between programs that are not related and, (c) it can identify and detect program variations, or code reuse. Such variations can be due to the insertion of malware (such as viruses) into the executable of a host program. The third technique improves the applicability of a semantic metamorphic malware detector which is the second technique of this dissertation. We propose an automated approach to generate common malware behavior patterns for detection of metamorphic malware or new malware instances. This method combines static analysis and data-mining techniques. This method has been prototyped and evaluated on real world malicious bot software and benign Windows programs. Through the experimental comparison with the metamorphic malware detector, this method results in an about 80% reduction in semantic pattern population to detect known and new malware instances. It is more robust to a junk behavior pollution attack than the malware detector is. A set of experiments was performed to test the quality of the common behavior patterns which were generated with different parameter configurations. Two optimized common behavior patterns were obtained. The corresponding detection rates and true false positive rates are 94%, 8.3%, and 78%, 0.32% respectively. According to a recent paper [1], for indirect comparison and simple reference, the values of the two detection rates which are 94% and 78% more than double the detection rate of signature-based methods on unknown malware programs, which is 33.75%.
Slipstream Processors
(2003-07-17) Purser, Zachary Robert; Eric Rotenberg, Committee Chair; Gregory T. Byrd, Committee Member; Thomas M. Conte, Committee Member; S. Purushothaman Iyer, Committee Member
Processors execute a program's full dynamic instruction stream to arrive at its final output, yet there exist shorter instruction streams that produce the same overall effect. This thesis proposes creating a shorter but otherwise equivalent version of the original program by removing ineffectual computation and computation related to highly-predictable control flow. The shortened program is run concurrently with and slightly ahead of a full copy of the program on a chip multiprocessor (CMP) or simultaneous multithreading (SMT) processor. The leading program passes all of its control-flow and data-flow outcomes to the trailing program for checking. This redundant program arrangement provides two key benefits. 1) Improved single-program performance. The leading program is sped up because it retires fewer instructions. Although the number of retired instructions is not reduced in the trailing program, it fetches and executes instructions more efficiently by virtue of having near-oracle branch and value predictions from the leading program. Thus, the trailing program is also sped up in the wake or 'slipstream' of the leading program, at the same time validating the speculative leading program and redirecting it as needed. Slipstream execution using two processors of a CMP substrate outperforms conventional non-redundant execution using only one of the processors. Likewise, given a sufficiently reduced leading program, slipstream execution using two contexts of an SMT substrate outperforms conventional non-redundant execution using only one of the contexts. 2) Fault tolerance. The shorter program is a subset of the full program and this partial redundancy is exploited for detecting and recovering from transient hardware faults. This does not require any additional hardware support, since the same mechanisms used to detect and recover from misspeculation in the leading program apply equally well to transient fault detection and recovery. In fact, there is no way to distinguish between misspeculation and faults. The broader rationale for slipstream is extending, not replacing, the capabilities of CMP/SMT processors, providing additional modes of execution. This thesis demonstrates the feasibility and benefits of the slipstream execution model.
A System for Managing User Obligations
(2009-12-05) Irwin, Keith; S. Purushothaman Iyer, Committee Member; Munindar P. Singh, Committee Member; Ting Yu, Committee Chair; Ping Ning, Committee Member
As computer systems become a more pervasive part of our societies, actions within those computer systems are becoming increasingly governed by complex policies such as laws, corporate policies, and legal agreements such as data sharing agreements and privacy policies. These policies impose both requirements about what may or may not be done and about what must be done. Current security policies may be able to manage restrictions on actions, but they are not sufficient to describe actions which are required. We examine herein the idea of user obligations, which are actions which are required of the users, but which the system cannot directly cause to occur. We propose a system for the management of user obligations. This system should both ensure that obligations are assigned in a manner such that it will be possible for them to be fulfilled and allow users of a system to know what they are required to do. We present an abstract formal model of such a system. We examine a number of aspects of such a system, principally including the maintenance of an acceptable system state, the assignment of blame when users fail to fulfill their obligations, and providing adequate feedback to users when their actions are rejected. For each of these aspects, we present formal definitions to define the range of acceptable behavior. We also provide a more specific and concrete model of one possible user obligations management system and develop algorithms for that model. We do this in order to show the practicality of our formal models and properties.
Using Performance Bounds to Guide Code Compilation and Processor Design
(2003-07-10) Zhou, Huiyang; Thomas M. Conte, Committee Chair; Gregory T. Byrd, Committee Member; Eric Rotenberg, Committee Member; S. Purushothaman Iyer, Committee Member
Performance bounds represent the best achievable performance that can be delivered by target microarchitectures on specified workloads. Accurate performance bounds establish an efficient way to evaluate the performance potential of either code optimizations or architectural innovations. We advocate using performance bounds to guide code compilation. In this dissertation, we introduce a novel bound-guided approach to systematically regulate code-size related instruction level parallelism (ILP) optimizations, including tail duplication, loop unrolling, and if-conversion. Our approach is based on the notion of code size efficiency, which is defined as the ratio of ILP improvement over static code size increase. With such a notion, we (1) develop a general approach to selectively perform optimizations to maximize the ILP improvement while minimizing the cost in code size, (2) define the optimal tradeoff between ILP improvement and code size overhead, and (3) develop a heuristic to achieve this optimal tradeoff. We extend our performance bounds as well as code size efficiency to perform code-size-aware compilation for real-time applications. The profile independent performance bounds are proposed to reveal the criticality for each path in a task. Code optimizations can then focus on the critical paths (even at the cost of non-critical ones) to reduce the worst-case execution time, thereby improving the overall schedulability of the real-time system. For memory intensive applications featuring heavy pointer chasing, we develop an analytical model based on performance bounds to evaluate memory latency hiding techniques. We model the performance potential of these techniques and use the analytical results to motivate an architectural innovation, called recovery-free value prediction, to enhance memory level parallelism (MLP). The experimental results show that our proposed technique improves MLP significantly and achieves impressive speedups.