Browsing by Author "Veena Misra, Committee Member"

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Amorphous Indium Gallium Zinc Oxide Thin-Film Transistors, Non-volatile Memory and Circuits for Transparent Electronics
(2010-06-26) Suresh, Arun; Leda lunardi, Committee Member; Mark Johnson, Committee Member; Veena Misra, Committee Member; John Muth, Committee Chair
The ability to make electronic devices, that are transparent to visible and near infrared wavelength, is a relatively new field of research in the development of the next generation of optoelectronic devices. A new class of inorganic thin-film transistor (TFT) channel material based on amorphous oxide semiconductors, that show high carrier mobility and high visual transparency, is being researched actively. The purpose of this dissertation is to develop amorphous oxide semiconductors by pulsed laser deposition, show their suitability for TFT applications and demonstrate other classes of devices such as non-volatile memory elements and integrated circuits such as ring oscillators and active matrix pixel elements. Indium gallium zinc oxide (IGZO) is discussed extensively in this dissertation. The influence of several deposition parameters is explored and oxygen partial pressure during deposition is found to have a profound effect on the electrical and optical characteristics of the IGZO films. By optimizing the deposition conditions, IGZO TFTs exhibit excellent electrical properties, even without any intentional annealing. This attribute along with the amorphous nature of the material also makes IGZO TFTs compatible with flexible substrates opening up various applications. IGZO TFTs with saturation field effect mobility of 12 â€“ 16 cm2 V-1 s-1 and subthreshold voltage swing of < 200 mV decade-1 have been fabricated. By varying the oxygen partial pressure during deposition the conductivity of the channel was controlled to give a low off-state current ~ 10 pA and a drain current on/off ratio of > 1 x108. Additionally, the effects of the oxygen partial pressure and the thickness of the semiconductor layer, the choice of the gate dielectric material and the device channel length on the electrical characteristics of the TFTs are explored. To evaluate IGZO TFT electrical stability, constant voltage bias stress measurements were carried out. The observed logarithmic dependence of the threshold voltage shift to the stress duration was modeled using a charge trapping/tunneling mechanism at the semiconductor/dielectric interface. By incorporating platinum nanoparticles in the dielectric layer of the TFT, non-volatile memory characteristics were achieved. The devices exhibited good memory behavior and up to 10 % charge retention extrapolated over 10 years. The potential application for IGZO TFTs is examined by fabricating and characterizing 5- and 7-stage ring oscillators. The 5-stage ring oscillators operate at more than 2 MHz and have a sub 50 ns propagation delay at a supply voltage of 25 V. To the best of our knowledge these are the fastest all-transparent ring oscillators reported to date. As a practical demonstration, we integrated IGZO TFTs with a novel thin film electroluminescent phosphor to form an active matrix pixel element. The output intensity of the phosphor was successfully modulated by the TFT. These results demonstrate that IGZO TFTs are viable candidates for transparent circuits and display applications.
Breakdown and Reliability of CMOS Devices with Stacked Oxide/Nitride and Oxynitride Gate Dielectrics Prepared by RPECVD
(2003-06-09) Lee, Yi-Mu; Carlton Osburn, Committee Co-Chair; Gerald Lucovsky, Committee Co-Chair; John Hauser, Committee Member; Veena Misra, Committee Member
Remote-plasma-enhanced CVD (RPECVD) silicon nitride and silicon oxynitride alloys have been proposed to be the attractive alternatives to replace conventional oxides as the CMOS logic and memory technology node is scaled beyond 100 nm. This dissertation is focused on the degradation and breakdown of RPECVD stacked oxide/nitride (O/N) and oxynitride gate dielectrics under constant-current stress (CCS) and constant-voltage stress (CVS). By monitoring the time-to-breakdown of the dielectrics, the device reliability can be determined and further used to evaluate the dielectric quality and the scaling limits of the dielectric thickness. It is found that the breakdown behavior of the gate oxide and RPECVD gate dielectrics is influenced by the degree of boron penetration, which in turn leads to increases in the gate leakage current. During electrical stresses, positive charges and hole trapping are generated at the Si/SiO2 interface and also in the dielectric layer, resulting in device degradation and final breakdown. We successfully use the RPECVD technique to incorporate an ultrathin (~0.6 nm) interfacial oxide layer and one monolayer of nitrogen in the gate stacks to improve the interface properties. Therefore, the stress-induced charges and trapping are suppressed and the device performance including SILC, threshold voltage instability, drive current and switching characteristics is improved. In addition, shorter-channel devices show more degraded electrical properties compared to longer-channel devices due to the increased damaged region in the gate-drain overlap near the channel. The TDDB reliability and lifetime of MOS devices with RPECVD O/N gate dielectric for the foreseeable mobile application are also investigated. This study is the first to reveal the trend of Weibull slopes and activation energy of O/N gate stacks. It has been found that Poisson area scaling is valid for O/N gate stack, indicating that the intrinsic breakdown is a random process and can be explained by the percolation model. Also, the voltage and temperature acceleration parameters are determined from TDDB. The projection of device lifetime based on total chip area and low percentile failure rate is demonstrated. The maximum tolerable operating voltage for a total gate area of 0.1 cm2 and 0.01% failure rate at 125° C is projected to be 1.9 V for 2.07 nm stacked O/N gate dielectrics.
A Chopper Modulated Amplifier System Design for in vitro Neural Recording
(2006-08-07) Dagtekin, Mustafa; Griff L. Bilbro, Committee Member; Robert J. Trew, Committee Chair; Robert M. Grossfeld , Committee Member; John M. Wilson, Committee Member; Veena Misra, Committee Member
Neural recording systems measure very low-amplitude signals of less than 5 kHz bandwidth. Low-frequency noise processes such as flicker noise and DC offset can degrade the quality of recordings made by such systems. A chopper modulated amplifier system is described and shown to reduce the flicker noise in neural recording systems by 10 to 20 dB. The amplifier system was implemented using the MOSIS ABN 1.5 micron technology. While the amplifier system contained an imperfection that prevented it from working with actual tissue samples, it worked well enough to prove that chopper modulation does reduce flicker noise appreciably. All of the details are presented along with studies of gate-metal-free transistors and custom-made MOSIS-based recording electrodes.
Circuit and Integration Technologies for Molecular Electronics
(2005-06-07) Nackashi, David Peter; John F. Muth, Committee Member; Veena Misra, Committee Member; Paul D. Franzon, Committee Chair; Gregory N. Parsons, Committee Member
Methods for fabricating a 2D array of gold nanoparticles were investigated for the purpose of creating a cross-linked molecular network. A controllable process for quickly and easily depositing and patterning regions of gold nanoparticles was developed. This process involves first patterning gold electrodes used for electrical measurement on the wafers. Regions are then defined in photoresist where the dense gold nanoparticles are desired. Finally, the nanoparticles are deposited using a short evaporation, resulting in island formation through the Volmer-Weber growth mechanism. The resist is then stripped in a process known as liftoff, and the result is a wafer-scale substrate with well-defined regions for molecular interconnect. Before assembly, these structures conduct less than 110pA of current at submicron electrode gap distances, and often less than 20pA. As determined from SEM image analysis, it is possible to quickly and easily deposit and pattern regions on silicon dioxide containing over 4,100 per um2, each with an average area of approximately 80nm2. The number of particles, average area and fill density can be controlled to allow for a number of applications and at a variety of scales. The smaller, more numerous particles integrate into sub-500nm gaps, and the larger, meandering lines integrate into micron-scale structures.
Computing with Novel Floating Gate Devices.
(2010-12-13) Schinke, Daniel; Paul Franzon, Committee Chair; William Davis, Committee Member; Veena Misra, Committee Member; Claude Reynolds Jr, Committee Member
Device Fabrication and Characterization for Alternative Gate Stack Devices
(2003-06-04) Kim, Indong; Carlton M. Osburn, Committee Chair; John R. Hauser, Committee Member; Veena Misra, Committee Member; Jon-Paul Maria, Committee Member
Aggressive scaling has continued to improve MOSFET transistor performance. An effective oxide thickness (EOT) less than 1.0nm is required for future technology nodes. However, tunneling currents of SiO2 become quite prominent below 1.5nm, leading to high leakage current. High-K dielectrics are required to reduce this leakage. A thicker dielectric reduces the probability of electron and/or hole tunneling through the gate dielectric and therefore the tunneling current. The use of metal gate electrodes is one of the technologies assumed in ITRS roadmap to circumvent the high sheet resistance and depletion associated with poly-Si gates. This dissertation covers the following research areas. First, projections of gate leakage currents for future ITRS nodes were made. High-K dielectrics which dramatically lower leakage will be needed for low standby power applications around year 2005. Secondly, NMOS and PMOS devices with alternative gate stacks were fabricated and evaluated using a new non-self aligned process. PVD HfO2 with an equivalent oxide thickness of 1.2 nm had a channel mobility comparable to SiO2. The effect of post metallization annealing of devices having PVD HfO2 was studied. Forming gas (10% H2 / 90% N2) annealing at 400° C enhanced drive current and channel mobility for devices having 1.2nm HfO2 gate dielectrics by eliminating interface states. PMA using 10% deuterium for 1.2nm HfO2 gate dielectrics resulted in larger enhancement drive currents and device channel mobility as compared to forming gas anneals. The stability of poly-Si gated HfO2 (~1.2nm EOT) dielectrics was also assessed after constant current stressing of the gate. The changes in device properties were measured as a function of stress time and stress current. With forming gas annealed HfO2, positive shifts in the threshold voltage exhibited a power law dependence on the injected charge (ΛVt ∝ QINJ 0.1). Finally, the properties of dilute Hf silicate were studied. A leakage minima was found at an intermediate Hf silicate (45~75% HfO2) composition. Nitirdation inhibited oxygen diffusion through Hf silicate dielectrics, and resulted in lower EOTs (10% lower) for nitrided samples.
Electrical Conductivity of Graphene Composites with Indium and Indium Gallium Alloy.
(2010-10-25) Avasarala, Naga Sruti; Jagannadham Kasichainula, Committee Chair; Veena Misra, Committee Member; Ronald Scattergood, Committee Member
Epitaxial Oxide Growth on Si(001) for Floating Epitaxy, a Novel Process for Silicon-on-Insulator Wafer Production
(2007-03-08) Hydrick, Jennifer Marie; Angus Kingon, Committee Chair; Veena Misra, Committee Member; Mark Johnson, Committee Member
As scaling continues in the semiconductor industry, silicon-on-insulator (SOI) wafers are increasingly becoming the substrate of choice, due to higher channel mobility, effective device isolation, reduced short channel effects, minimized parasitic capacitance, and therefore higher speed, compared to a regular silicon wafer. Current methods of SOI wafer production, however, will have difficulty achieving the desired silicon device layer and buried oxide insulator layer thicknesses and eliminating interface roughness as scaling proceeds. We propose "Floating Epitaxy SOI" as a novel method of SOI production utilizing an all in-situ growth process. Floating Epitaxy SOI involves Molecular Beam Epitaxy deposition of an epitaxial template oxide, oxidizing through the epitaxial template layer to establish the insulation layer, and silicon growth on top of the epitaxial template oxide layer (which is now "floating" on top of an amorphous oxide layer). The key to this process is the epitaxial oxide template layer, which must deposit on the silicon substrate as an atomically smooth film with a lattice parameter close to that of silicon and must be sufficiently stable in both an oxygen an in vacuum annealing to relatively high temperature to achieve Floating Epitaxy SOI. Although many researchers have examined epitaxial oxides on silicon, this study focuses on epitaxial films over large area substrates, while virtually all other studies report on growth on small substrate sizes. Also, the oxide stability limits on silicon in vacuum have not been thoroughly established by previous work, and are investigated here. The growth and thermal stability of this epitaxial oxide template layer are discussed, as well as brief results for through-oxidation "floating" of the template oxide layer and silicon growth experiments. BaO, SrO, CaO, Ba[subscript 1-x]Sr[subscript x]O, SrTiO₃, CaTiO₃, and Ca[subscript 1-x]Sr[subscript x]TiO₃ were successfully epitaxially deposited on Si(001) substrates. A 64:36 Ba:Sr ratio was used for the solid solution of Ba[subscript 1-x]Sr[subscript x]O, in order to achieve close lattice matching with silicon; a 50:50 Ca:Sr ratio was used initially for the Ca[subscript 1-x]Sr[subscript x]TiO₃ solid solution, an attempt to mediate SrTiO₃'s 2% lattice mismatch with silicon and CaTiO₃'s orthorhombic structure. Alloying SrTiO₃ with calcium to alter the lattice parameter has not been studied much to this point in thin films, and this is the first demonstration of Ca[subscript 1-x]Sr[subscript x]TiO₃ and CaTiO₃ thin films grown directly on silicon. Reflection High Energy Electron Diffraction patterns of both Ba[subscript 1-x]Sr[subscript x]O and Ca[subscript 1-x]Sr[subscript x]TiO₃ indicated high quality 2D epitaxial films. A thin (3 monolayer) film of Ba[subscript 1-x]Sr[subscript x]O is stable on silicon to 535°C in vacuum, while a 5 monolayer Ca[subscript 1-x]Sr[subscript x]TiO₃ film survives to 740°C in vacuum, but roughens from a 2D toward a 3D surface above ˜650°C. Of the epitaxial oxides studied, the solid solution Ca[subscript 1-x}Sr[subscript x]TiO₃ would be the best choice for Floating Epitaxy SOI, based on epitaxial growth quality and stability. High-resolution TEM indicates the presence of an amorphous interfacial layer at the SrTiO₃Si interface, as grown. X-ray diffraction confirms an epitaxial film, with a lattice parameter larger than that of bulk SrTiO₃, likely due to oxygen deficiency in the film. Annealing 17.5nm SrTiO₃Si(001) at 800°C in 5.5 Torr of oxygen for 30 minutes results in an equivalent oxide thickness of 10.3nm, sufficient for scaling to 2020. X-ray diffraction after annealing reveals a still-epitaxial SrTiO₃ film, with sharper 2θ and χ peaks and a lattice parameter closer to that of bulk SrTiO₃. These results validate the "floating" epitaxy approach: an epitaxial film remains on top of an amorphous insulator, after through-oxidation of the substrate. Direct deposition of epitaxial silicon on Ca[subscript 1-x]Sr[subscript x]TiO₃ and solid-phase epitaxy of silicon on a CaTiO₃ film are promising, but interface engineering or a surfactant may be required to achieve a high quality, single crystal silicon layer.
Fabrication and Characterization of Electrical Contacts for Charge Transport Study in Molecular Electronics.
(2006-09-29) Chu, Changwoong; Veena Misra, Committee Member; Orlin D. Velev, Committee Member; Gregory N. Parsons, Committee Chair; Christine S. Grant, Committee Member
Nanoscale imprint lithography (NIL) is investigated in the view point of the ability to form nanoscale feature. NIL at room temperature is proposed and demonstrated on thermoplastic substrate that has a restriction of heating. Anisotropic oxygen-based plasma etch performance is evaluated to remove the residual resist at the bottom of impressed pattern and to achieve the thinner patterns with various etching molecules. The patterning fidelity in nano-imprint lithography including the ability of polymer deformation is studied, and based on the results a mechanism for the polymeric behavior of imprinted resist is discussed. A procedure using geometrical shadowing in common metal-evaporation tools to form nanoscale metal electrodes with controlled width-to-pitch ratios is demonstrated and characterized for feature sizes near 50 nm. Successive formation of metallic bridge with the metallic nanoparticle for the conductance study and the electrical characterization are described. From the results of electrical conduction, we estimate the contact area (~20.1 nm2) and the number of molecules between nanoparticle and surface-bound molecules, and then calculate the resistances of single molecules, contact resistance, the tunneling probabilities in contacts. The electrical characterization of the conjugated molecules has been accomplished using the same nanoscale test-bed in terms of surface bound head groups. As a new approach for the interconnecting elementary molecular devices, Au nanoparticle dimer bridged by conjugated molecule is assembled on the nanoscale electrode gap. Oligo Phenylacetylene-bridged gold nanoparticle dimer was prepared for the demonstration. Resistance measured at low bias regime is 2.2 ± 0.64 GΩ at room temperature, which is comparable with the single molecule conduction. The selective adsorption of SAM on Au plates by means of electron supply is proposed to develop the pliable manipulation of self-assembling molecular elementary devices. The method is applied to the two metal patterns, which is an electrical test-bed for the molecular resistors. The electrical characterization is in good agreement with the selective formation of molecular layer on metal.
Formation of Low-Resistivity Germanosilicide Contacts to Phosporous Doped Silicon-Germanium Alloy Source/Drain Junctions for Nanoscale CMOS
(2003-12-30) Mo, Hongxiang; Douglas Barlage, Committee Member; Gregory Parsons, Committee Member; Mehmet Ozturk, Committee Chair; Veena Misra, Committee Member
Conventional source/drain junction and contact formation processes can not meet the stringent requirements of future nanoscale complimentary metal oxide silicon (CMOS) technologies. The selective Si[subscript 1-x]Ge[subscript x] source/drain technology was proposed in this laboratory as an alternative to conventional junction and contact schemes. The technology is based on selective chemical vapor deposition of in-situ boron or phosphorus doped Si[subscript 1-x]Ge[subscript x] in source/drain areas. The fact that the dopant atoms occupy substitutional sites during growth make the high temperature activation anneals unnecessary virtually eliminating dopant diffusion to yield abrupt doping profiles. Furthermore, the smaller band gap of Si[subscript 1-xGe[subscript x] results in a smaller Schottky barrier height, which can translate into significant reductions in contact resistivity due to the exponential dependence of contact resistivity on barrier height. This study is focused on formation of self-aligned germanosilicide contacts to phosphorous-doped Si[subscript 1-x]Ge[subscript x] alloys. The experimental results obtained in this study indicate that self-aligned nickel germanosilicide (NiSi[subscript 1-x]Ge[subscript x]) contacts can be formed on Si[subscript 1-x]Ge[subscript x] layers at temperatures as low as 350°C. Contacts can yield a contact resistivity of 1E-8 ohm-cm² with no sign of germanosilicide induced leakage. However, above a threshold temperature determined by the Ge concentration in the alloy, the NiSi[subscript 1-x]Ge[subscript x]/Si[subscript 1-x]Ge[subscript x] interface begins to roughen, which affects the junction leakage. For phosphorus doped layers considered in this study, the threshold temperature was around 500°C, which is roughly 100°C higher than the threshold temperature for NiSi[subscript 1-x]Ge[subscript x contacts formed on boron doped Si[subscript 1-x] Ge[subscript x] layers with a Ge percentage of ~ 50%. Nickel and zirconium germanosilicides were also considered as contact candidates but they were found to result in a contact resistivity near 1E-7 ohm-cm².
Integrated Single Pole Double Throw (SPDT) Vertical Power MOSFETs for High Current and Fast Frequency Monolithic Synchronous Converters
(2010-08-10) Jung, Jeesung; Alex Q. Huang, Committee Chair; Kevin G. Gard, Committee Member; Veena Misra, Committee Member; Subhashish Bhattacharya, Committee Member
The SPDT switch is implemented by two integrated vertical-structure power MOSFETs for the first time. In other words, a high current handling monolithic synchronous converter, based on both a control and a synchronous vertical MOSFET structure is proposed. The power switches are designed as combining the advantages of both conventional lateral- and vertical-type MOSFETs. Therefore, the lowest FOMs among the same voltage-rating devices as well as the high operating current handling capability have been achieved. Besides, various integrated devices such as analog/digital Complementary Metal Oxide Semiconductor(CMOS)s and Bipolar Junction Transistor(BJT)s show good performances as power stage driver and controller ones at the same time. In addition, the new monolithic design challenges such as isolations and parasitic devices are addressed and possible solutions are verified not only by state of the art device/circuit simulations but also by experiments. The new concept of the controlled CMOS p-body voltage which can subdue the parasitic effects dramatically and increase the reliability providing full flexibility of integration is explained, also. Eventually, novel BCD(Bipolar-CMOS-DMOS) process which is optimized to achieve all goals above is developed. And the most challengeable none-standard CMOS process of the current path-trench fabrication is investigated in details and tested physically and electrically. Though the buck converter is selected and analyzed in details in this dissertation due to its popularity, the proposed SPDT switch can be used for other SMPS(Swith Mode Power Supply) converters such as a boost or a buck-boost converter, also. Therefore, this dissertation should build a strong motivation for the practical implementation of the new SOC(System On a Chip)-high current and fast frequency handling power converter design for the first time.
Integration of VO2 Films on Al2O3 and Si (100) Substrates: Structure-Property Correlations and Applications.
(2011-01-31) Yang, Tsung-Han; Jagdish Narayan, Committee Chair; Veena Misra, Committee Member; Jerome Cuomo, Committee Member; John Prater, Committee Member
Interface reactions during processing of chemical vapor deposited yttrium oxide high-k dielectrics
(2002-11-28) Niu, Dong; H. Henry Lamb, Committee Member; Gerald Lucovsky, Committee Member; Veena Misra, Committee Member; Gregory N. Parsons, Committee Chair
High dielectric constant (high-k) insulators are important for advanced MOS devices to limit gate leakage and increase gate capacitance. Reactions between high-k's and the substrate during deposition or post-deposition processing lead to an increase in the equivalent oxide thickness, and the mechanisms that control the changes need to be well understood. We investigate yttrium-based high-k dielectrics formed by oxygen plasma assisted CVD on Si(100), using two different yttrium diketonate precursors. Characterization techniques include IR, XPS, TEM, EELS, AES, and IV and CV electrical analysis. During deposition and post-deposition anneals a thin Y-O-Si (silicate)/SiO₂ structure due to intermixing of Y, O and Si and substrate oxidation is formed at the interface, between the Y₂O₃ and silicon. The extent of the intermixing depends on substrate surface preparation, process conditions, and annealing conditions. As-deposited Y₂O₃ films show evidence for O-H bond due to water absorption. With in-situ deposited Si capping layers, water pickup is significantly reduced, and interfacial SiO₂ layer after annealing is less than 5 Å. Analysis of reaction mechanisms suggests that Si diffusion is attributed to silicate formation, and water absorption, catalytic dissociation of residual O₂, and O₂ plasma may account for SiO₂ formation. Nitridation of chemical vapor deposited yttrium oxide using N₂ plasma during deposition and post-deposition treatments is investigated. The use of N₂ instead of O₂ during deposition minimizes the substrate oxidation. Similar activation energies for post-deposition anneals of O₂ and N₂ films indicate substrate oxidation processes are likely the same. Bulk properties including chemical bonding, concentration and distribution of N are also studied for as-deposited and annealed films.
Low Resistivity Contact Methodologies for Silicon, Silicon Germanium and Silicon Carbon Source/Drain Junctions of Nanoscale CMOS Integrated Circuits.
(2009-12-03) Alptekin, Emre; Mehmet C. Ozturk, Committee Chair; Thomas P. Pearl, Committee Member; Michael Escuti, Committee Member; Veena Misra, Committee Member
State-of-the-art p-channel metal oxide semiconductor field effect transistors (MOSFETs) employ Si(1-x)Ge(x) source/drain junctions to induce uniaxial compressive strain in the channel region in order to achieve hole mobility enhancement. It is also know that the elec- tron mobility can be enhanced if the MOSFET channel is under uniaxial tension, which can be realized by replacing Si(1-x)Ge(x) with Si(1-y)C(y) epitaxial layers in recessed source/drain regions of n-channel MOSFETs. This dissertation focuses on epitaxy of Si(1-y)C(y) layers and low resistivity contacts on Si, Si(1-x)Ge(x), and Si(1-y)C(y) alloys. While these contacts are of particular importance for future MOSFETs, other devices based on these semiconductors can also benefit from the results presented in this dissertation. The experimental work on Si(1-y)C(y) epitaxiy focused on understanding the impact of various process parameters on carbon incorporation, substitutionality, growth rate, phosphorus incorporation and activation in order to achieve low resistivity Si(1-y)C(y) films with high substitutional carbon levels. It was shown, for the first time, that phosphorus lev- els above 1.3x10^(21) cm^(-3) can be achieved with 1.2% fully substitutional carbon in epitaxial layers. Specific contact resistivity (C) on strained Si(1-x)Ge(x) layers was evaluated using the existent results from the band structure calculations. Previous work on this topic mainly focused on barrier height and the doping density at the interface. In this work, the impact of the tunneling effective mass on specific contact resistivity was calculated for the first time for strained Si(1-x)Ge(x) alloys. It was shown that due to the exponential dependence of contact resistivity on this parameter tunneling effective mass may have a strong impact on contact resistivity. This is especially important for strained alloys in which the tunneling effective mass is dependent on the strain. The contact resistivity was found to decrease with Ge concentration due to the smaller tunneling effective mass in strained Si(1-x)Ge(x). These calculations can also be extended to Si(1-y)C(y) junctions when better models for the Si(1-y)C(y) band structure are available. Two different metallization schemes have been considered. In the first approach, two band edge silicides are used to achieve low-resistivity contacts on complimentary MOSFETs. For this purpose, experiments on band edge silicides including PtSiGe, NiSiC and ErSiC were conducted. The impact of Ge and C on silicide formation and the barrier height at the interface was investigated. Barrier height values around 0.3 eV were achieved with PtSiGe and ErSiC contacts formed on p-Si(1-x)Ge(x)and n-Si(1-y)C(y), respectively. Due to the exponential dependence of contact resistivity on barrier height, this barrier height is low enough to yield contact resistivity figures below 10^(-8) Ohm-cm^(2) even with modest doping levels. On the other hand, smaller barrier height values will be needed for Schottky barrier MOSFETs. It is more desirable to use a single metal contact metal on both p- and n-channel MOSFETs, which requires tuning of the barrier height. Impurity implantation was considered as a means to achieve barrier height tuning. Extremely small barrier height values below 0.1 eV were obtained by sulfur segregation for the silicides of Pt, Ni and NiPt on n-type Si and Si(1-y)C(y). Indium segregation was used for the first time to lower the hole barrier height to obtain barrier height values below 0.2 eV on p-Si. The results provide several approaches that can be used to form low resistivity contacts. We believe that the knowledge gained from this work is expected to have a significant impact on choosing the most effective and economical approach to form low-resistivity contacts in CMOS manufacturing.
Micro-stimulator design for Retinal Prostheses
(2004-02-07) Singh, Praveen Rajan; Wentai Liu, Committee Chair; Gianluca Lazzi, Committee Member; Veena Misra, Committee Member
The purpose of this research is to design an integrated circuit (IC) to stimulate retina. The IC will be able to generate electrical stimulus specified by medical researchers. The IC is to be low power and low area, as it has to be implanted inside the eye. Specified area goal is to provide 1000 outputs in 5mm x 5mm implementation. Analysis is done to understand and explain the theory for power reduction. To provide large number of stimulus outputs, improvements in the previous design have been made. A number of circuits have been proposed to attain better performance. New circuit designs include active feedback output stage, design in advance process technology (TSMC 0.35 μm), variable power supply, better linearity, charge cancellation, variable output range and DAC. Layouts have been made to meet the area goals. A test chip was fabricated in AMI 1.6 μm. Measurement results have been found to be as predicted.
Molecular Electronic Memories
(2006-03-27) Amsinck, Christian Johannes; Paul Franzon, Committee Chair; Veena Misra, Committee Member; John Muth, Committee Member; Gregory Parsons, Committee Member
The feasibility of building large memories using molecular electronic devices with bistable conductance-state memory has been investigated. A novel fabrication method for twoterminal molecular memory devices that is integrateable into large-scale arrays while avoiding top-contact evaporation on a molecular monolayer has been developed. A sacrificial layer underneath the top contact metal is wet-etched to create free-standing cantilevers in aqueous solution and a self-assembled monolayer is formed on the underside of the cantilever. Subsequent atmospheric drying causes the freestanding structure to become permanently adhered to the substrate, resulting in a two-terminal molecular structure. This device has been investigated with alkanethiol monolayers as a proof-ofconcept, and the expected decrease in current with increasing chain length is observed. The measured current density in control devices without molecules is also consistent with models of loaded cantilevers. Previously characterized molecules exhibiting memory behavior were also investigated and demonstrated bistable memory effects similar to earlier observations. The scalability of such bistable molecular memory devices was analyzed from a circuits perspective, and the impact of different system parameters was quantified. It is necessary to build large arrays with at least several hundred molecular memory cells along each dimension, in order to prevent peripheral circuitry from dominating the area. It is quantitatively shown how this requirement constrains the minimum allowable forward⁄reverse-bias rectification ratio of the molecular devices, as well as the minimal on⁄off ratio of the two molecular conductance states. The parasitic wiring impedance is negligible in the case of metallic interconnect, but the impedance of currently available molecular wires makes large-scale all-molecular arrays infeasible.
On-Chip Manipulation and Controlled Assembly of Colloidal Particles using Alternating Electric Fields
(2006-05-15) Bhatt, Ketan Harendrakumar; Saad Khan, Committee Member; Jan Genzer, Committee Member; Veena Misra, Committee Member; Orlin Velev, Committee Chair
Alternating (AC) electric fields have been investigated as a versatile tool for rapid particle and fluid manipulation in micro- Total Analysis Systems (μTAS). Different on-chip electrode geometries and different particle suspensions were explored in this study with an aim to acquire a fundamental understanding of particle behavior under applied fields. Aqueous suspensions of particles of sizes ranging from nanoparticles to microspheres and having varied electrical properties (dielectric or conductive) were studied. For each system, detailed electrostatic simulations were carried out to identify the forces acting on the particles and fluid. Control of the particle-field, fluid-field and particle-particle interactions, by fine tuning the applied field, lead to the desired assembly of particles. Dielectrophoresis (DEP) was used to assemble gold nanoparticles into microwires and for manipulating fluid droplets containing suspended particles. AC Electrohydrodynamics (EHD) driven liquid flows were used for the transportation, redistribution and collection of suspended particles inside experimental cells. Suspensions of metallic nanoparticles in water were assembled via DEP into wires of micrometer thickness between planar electrodes. Control of the process parameters allowed making, for example, straight single connectors, or massively parallel arrays of microwires on the surface of the chip. The direction of microwire growth was guided by introducing conductive islands or particles in the suspension. DEP based manipulation of freely suspended droplets was used for designing a novel liquid-liquid microfluidic chip. Water droplets containing suspended particles were floated on dense fluorinated oil and manipulated by applying electric fields using electrodes present beneath the oil. The on-chip system was capable of transporting multiple droplets in parallel, for rapid mixing of the contents of droplets and for carrying out chemical reactions and precipitations. AC fields were applied to dilute suspensions of latex microspheres enclosed between a patterned silicon wafer and an ITO-coated glass slide in a small chamber. The latex particles entrained by EHD flow became collected in the center of the conductive "corrals" on the silicon wafer. The particle collection efficiency and speed depended only on the frequency and strength of the field and were independent of the material properties of the particles or the electrodes.
Optimal Design of Vibration-based Energy Harvesting Systems using Magnetostrictive Material (MsM).
(2010-09-10) Hu, Jingzhen; Alex Huang, Committee Chair; Fuh-Gwo Yuan, Committee Chair; Paul Franzon, Committee Member; Veena Misra, Committee Member
Photoelectrocatalytic Sensor for Volatile Organic Compounds using Indium Gallium Zinc Oxide Thin Film Transistor.
(2010-11-01) Patil, Nishad; John Muth, Committee Chair; Veena Misra, Committee Member; Leda Lunardi, Committee Member
Photoemission Spectroscopic Studies of Metal-Gated MOS structures based on ultra-thin High-k Dielectrics
(2009-03-05) Choung, Jiyoung; Robert M. Kolbas, Committee Member; Veena Misra, Committee Member; John F. Muth, Committee Chair; Jack E. Rowe, Committee Member; Robert J. Nemanich, Committee Co-Chair
The band structure and interface properties of high-Îº MOS gate stack structures have been studied using a combination of x-ray and ultraviolet photoemission spectroscopy to comprehend the effective work function (EWF) variation during thermal processing. The possibility of controlling the effective work function of a metal by inserting an intentional dipole layer or additional charges is investigated using high-k gate stacks. The band bending of a Si interface and the electric field across the buffer oxide is explored using the band structure analysis of MOS capacitors. Prior to the band structure analysis of MOS capacitors, a high-Îº/buffer oxide (SiO2) on p- and n-Si substrates is explored to observe the Si band bending and the electric field across the buffer oxide, which demonstrates the possibility for control of the effective work function of a metal by inserting an intentional dipole layer or additional charges. The Fermi level alignment of TiN/HfO2/p- and n-type Si is investigated, where three main conclusions are presented: 1) the Fermi level difference between TiN/high-Îº/p- and n-type Si substrates has been identified with photoemission spectroscopy (XPS, UPS) and the results used to determine the band structure; 2) a systematic study of the core level spectra shifts of the Si 2p and Hf 4f display the Fermi level alignment; 3) the results indicate that the interfacial dipole at high-Îº/buffer oxide contributes to the EWF of TiN in the structure. To observe the effects depending on different dielectrics on the EWF, TiN on SiO2, HfO2, and Al2O3 is investigated, and the results are found to be similar to the results obtained by Capacitance Voltage measurements. Finally, the process and temperature dependence of a PMOS capacitor (Ru/HfSiOx/n-Si) is studied. The process dependence showed that there is a large gap between the VWF and the EWF of Ru after annealing, and the interface at the high-Îº/buffer oxide needs to be considered to tune the EWF. The temperature dependence revealed the thermal instability of Ru with HfSiOx over 700Â°C. This study suggests that the EWF is affected by the dipole layer not only at a metal/high-Îº interface but also at a high-Îº / SiO2 interface.