Browsing by Author "Veena Misra, Member"

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4H-SiC Trench-Gate MOSFET: Practical Surface-Channel Mobility Extraction.
(2019-08-23) Harmon, Jeffrey Lee; B. Baliga, Chair; Stephen Michielsen, Graduate School Representative; John Muth, Member; John Veliadis, Member; Veena Misra, Member
Amorphous Indium Gallium Zinc Oxide Based Thin Film Transistors and Circuits.
(2013-06-10) Luo, Haojun; John Muth, Chair; Leda Lunardi, Co-Chair; Mark Johnson, Member; Robert Kolbas, Member; Veena Misra, Member
Autonomous Thin Film Fabrication and In Situ Spectroscopy for Photovoltaic Applications.
(2024-08-23) Woodward, Nathaniel; Aram Amassian, Co-Chair; John Muth, Co-Chair; Veena Misra, Member; Reha Uzsoy, Member
Characterization and Analysis of Multi-Quantum Well Solar Cells.
(2014-05-09) Bradshaw, Geoffrey Keith; Salah M. Bedair, Chair; Nadia El-Masry, Member; Veena Misra, Member; Mehmet Ozturk, Member
Characterization of High-k Gate Stacks in Metal-Oxide-Semiconductor Capacitors
(2001-02-05) Li, Wenmei; Dennis M. Maher, Chair; John J. Hren, Member; Gerald Lucovsky, Member; Veena Misra, Member
The purpose of this research has been to use off-line characterization techniques to establish material-specific properties of gate-stack constituents (i.e., high-k dielectric stacks and electrodes) and complete gate-stack structures. Hence, the characterization methodologies were established to evaluate high-k dielectrics at various processing levels, which, in part, determine the final characteristics of an advanced gate-stack device. Material systems that were investigated include: Al-O, Hf-Si-O, Zr-Si-O, Ti-O, Ta-O and Sr-Ti-O. Various physical and electrical characterization techniques were used to establish fundamental understandings of the materials selected, thin-film growth/deposition processes, and gate-stack structures. General conclusions for stable and unstable gate-dielectric materials have been establishedregarding the presence of a problematic interfacial layer at the Si/dielectric interface, graded dielectric layers, and the stability of gate electrodes on high-k dielectrics.The nanometer-scale chemistry of a gate-stack capacitor whose expected structure is Si/SiOxNy/Ta2O5/TiN/Al was studied by high-resolution electron-energy-loss spectroscopy in a scanning transmission electron microscope. Elemental profiles with near-atomic-level resolution for Si, Ti, N, Al, and O demonstrate that the device structure deviates drastically from the expectation and is chemically complex.It is concluded that the graded distribution of certain elements across the gate-stack capacitor completely precludes a band-structure model that assumes abrupt interfaces and chemically discrete layers. This study impacted on subsequent interpretations of flatband voltage extractions and electrical degradation following backside metallization/postmetallization annealing for capacitors whose dielectric-stack was based on Ta-O.Detailed and extensive electrical characterizations of Pt/SiOx/Sr-Ti-O/Si MOS capacitors were carried out to investigate reliability issues in a bi-layer gate dielectric. Based on these studies, models are proposed to describe the carrier transport and dielectric degradation for a Sr-Ti-O capacitor. It is concluded that conduction is dominated by Frenkel-Poole emission from mid-gap trap levels. The trap barrier height is estimated to be 1.51eV. A model based on the atomic and electronic structure of oxygen vacancies can account for the reported leakage-current characteristics. In addition, it is tentatively proposed that anode-hole injection and hole trapping control the dielectric degradation under gate injection.
Charge and Spin Carrier Transport in Graphene and its Derivatives.
(2011-10-31) Borysenko, Kostyantyn; Ki Kim, Chair; Veena Misra, Member; David Aspnes, Member; John Muth, Member
Considerations for Electrical Characterization of MOS Capacitors that Arise Due to Processing
(2001-07-31) Schrader, Michael John; Richard Kuehn, Chair; Dennis Maher, Member; Veena Misra, Member
The goal of this research was to determine the effects thatthe actual physical structure of an overlapped metal-oxide-semiconducter (MOS) capacitor and an etch bias have on the extraction of the gate-oxide thickness. Included in these concerns were the overlap of the field oxide by the gate electrode, the angle of the active-area sidewall, and the increase in size of the active area due to an etch bias. In addition, the growth of a contaminant layer, or ad-layer,on oxides that do not have a permanent gate-electrode was addressed. This ad-layer forms immediately after a wafer is exposed to the lab ambient and causes a significant increase (i.e., ~ 10%) in the apparent thickness of the oxide.The refinement of the total capacitance to the active-area capacitance uses measured data from Hg-gated capacitors on p-type Si wafers and Al / Poly-Si gated capacitors on both p- and n-type Si wafers. The effects of a non-vertical sidewall and an etch bias are addressed theoretically through the use of the classic treatment of capacitance. The capacitance-voltage characteristics from the MOS capacitors were used to extract the oxide thickness (tox).The extracted thickness was determined from a model-based methodology (i.e., the slope method) and a model-based analysis (i.e., NCSU's CVC model). It is shown that the effect of a non-vertical sidewall and an etch bias are negligible. The effect of the gate electrode overlap, while small, should be removed. It is also shown that a model-based analysis of the active-area capacitance characteristics results in a consistent oxide thickness over the range of capacitor areas that were available.The removal and re-growth of the ad-layer were investigated using current-voltage and capacitance-voltage characteristics from blanket oxides on both p- and n-type silicon wafers. The changes in these characteristics were quantified as the ad-layer grows over time. The C-V characteristics were analyzed using NCSU's CVC program in order to extract values for oxide thickness, flatband voltage, and interface trap densities. The ad-layer causes considerable inaccuracies in the model extraction of oxide thickness as well as the flatband voltage and interface trap density. Electrical and optical results on the p-type wafer both show that the ad-layer increases the apparent oxide thickness by ~ 0.25 nm and the electrical results show that the ad-layer shifts the flatband voltage by as much as 100 mV.
Controlling the Shape and Interfacial Properties of Eutectic Gallium Indium.
(2012-07-27) So, Ju-Hee; Michael Dickey, Chair; John Muth, Member; Saad Khan, Member; Veena Misra, Member; Orlin Velev, Member
Design and Fabrication of 4H-SiC High Voltage Devices.
(2011-12-09) Sung, Woongje; Alex Huang, Co-Chair; B. Baliga, Co-Chair; Subhashish Bhattacharya, Member; Veena Misra, Member; Anant Agarwal, Member
Design and Fabrication of Glass-based Capacitive Micromachined Ultrasonic Transducers (CMUT) for Imaging, Neuro-stimulation, and Power Transfer.
(2023-11-03) Annayev, Muhammetgeldi; Omer Oralkan, Chair; Veena Misra, Member; Paul Dayton, Member; Feysel Yalcin Yamaner, External; Alper Bozkurt, Member
Design and Fabrication of High Voltage Silicon Carbide Symmetric Blocking Switch for FREEDM Smart Grid.
(2014-04-25) Huang, Xing; Alex Huang, Co-Chair; B. Baliga, Co-Chair; Mehmet Ozturk, Member; Stephen Michielsen, Graduate School Representative; Lin Cheng, Member; Veena Misra, Member
Development of High Resolution Depth Profiling of Ultra Shallow Dopant Implants with SIMS
(2001-07-02) Loesing, Rainer; Phillip E. Russell, Chair; Dieter P. Griffis, Member; Veena Misra, Member; J. Michael Rigsbee, Member
Secondary Ion Mass Spectrometry (SIMS) is considered a reliable technique for precise and accurate dopant depth profiling in Si with respect to junction depth and implanted dose. The junction depths of source drain extension structures are predicted to be between 19-33nm for the 0.1µm MOSFET generation. Accurate high depth resolution analysis of these ultra-shallow junctions by SIMS can only be provided if atomic mixing caused by energetic primary ion bombardment is minimized and extensive beam induced crater bottom roughening is avoided. For quantitative measurements, the influence of primary ion implantation, sputter rate changes and beam induced crater bottom roughness on secondary ion intensities has to be known. In this work SIMS was used to develop techniques for the accurate analysis of ultra shallow B, P and As implants in Si.Low energy O2+ primary ion bombardment was found to give the highest depth resolution for the analysis of B and P in Si, while low energy Cs+ and CsC6- primary ion bombardment resulted in the highest depth resolution for the analysis of As in Si. To obtain a more accurate profile shape and depth scale it was found to be essential to limit beam induced crater bottom roughness by means of sample rotation, variations of primary ion angle of incidence or change in sample chamber vacuum conditions. Beam induced crater bottom roughness was investigated for low energy O2+, Cs+ and CsC6- ion bombardment using atomic force microscopy (AFM) and optical profilometer (OP) measurements. OP was found to be a valuable tool for investigating small changes in sputter rate in the initial stages of a SIMS depth profile. It was shown that dose measurements of ultra shallow implants can be improved by using a correction procedure based on bulk doped standards. SIMS was proven to be a valuable tool for the characterization of ultra shallow implants in Si, but careful consideration of analysis conditions and SIMS artifacts is required for accurate analysis.
Enhancing Performance of SiC Planar-gate Power MOSFETs with 650 V, 1.2 kV, and 2.3 kV Blocking Voltages with Structural Modifications.
(2021-06-01) Agarwal, Aditi; B. Baliga, Chair; John Veliadis, Member; Subhashish Bhattacharya, Member; Ramon Collazo, Graduate School Representative; Veena Misra, Member
Equivalent Circuit Models for Radio Frequency Driven Plasma Source Design and Operation.
(2023-04-20) Smith, Jr., Carl Lynwood; Steven Shannon, Chair; Katharina Stapelmann, Member; Mohamed Bourham, Member; Veena Misra, Member
Fabrication of Amorphous Indium Gallium Zinc Oxide Thin Film Transistors by Focused Ion Beam
(2015-05-01) Zhu, Wencong; John Muth, Chair; Veena Misra, Member; David Aspnes, Member; Robert Kolbas, Member
Flexible Thermoelectric Energy Generators using Liquid Metal Interconnects, Bulk Thermoelectric Legs and Low Thermal Conductivity Elastomer.
(2019-08-05) Padmanabhan Ramesh, Viswanath; Mehmet Ozturk, Chair; Veena Misra, Member; Alper Bozkurt, Member; Philip Barletta, Member; Michael Dickey, Graduate School Representative
Flexible Thermoelectric Energy Harvesters Using Bulk Thermoelectric Legs and Low-Resistivity Liquid Metal Interconnects with High Thermal Conductivity Encapsulation
(2019-08-16) Sargolzaeiaval, Yasaman; Mehmet Ozturk, Chair; Veena Misra, Member; Alper Bozkurt, Member; Michael Dickey, Member
Impact of Process Variations on 16-nm Dual-floating Gate FET using TCAD Simulations.
(2012-12-18) Kotipalli, Venkata Satya Vinodh; Paul Franzon, Chair; Veena Misra, Member; Neil DiSpigna, Member
In-situ Sintering Decrystallization of Thermoelectric Materials using Microwave Radiation.
(2017-03-16) Nozariasbmarz, Amin; Daryoosh Vashaee, Chair; Mehmet Ozturk, Member; Veena Misra, Member; James LeBeau, Minor; James LeBeau, Graduate School Representative
Lab in a Brick: An Unobtrusive Unattended Sensor for Urban Environments.
(2014-01-31) Smith, James Edison; John Muth, Chair; Edward Grant, Member; Veena Misra, Member