Browsing by Author "Xun Liu, Committee Chair"

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Exploration of High-level Synthesis Techniques to Improve Computational Intensive VLSI Designs
(2009-12-07) Kim, Taemin; W. Rhett Davis, Committee Member; Eric Rotenberg, Committee Member; Xun Liu, Committee Chair; James M. Tuck, Committee Member
Optimization techniques during high level synthesis procedure are often preferred since design decisions at early stages of a design Ã¯Â¬â€šow are believed to have a large impact on design quality. In this dissertation, we present three high-level synthesis schemes to improve the power, speed and reliability of deep submicron VLSI systems. SpeciÃ¯Â¬Â cally, we Ã¯Â¬Â rst describe a simultaneous register and functional unit (FU) binding algorithm. Our algorithm targets the reduction of multiplexer inputs, shortening the total length of global interconnects. In this algorithm, we introduce three graph parameters that guide our FU and register binding. They are Ã¯Â¬â€šow dependencies, common primary inputs and common register inputs. We maximize the interconnect sharing among FUs and registers. We then present an interconnect binding algorithm during high-level synthesis for global intercon- nect reduction. Our scheme is based on the observation that not all FUs operate at all time. When idle, FUs can be reconÃ¯Â¬Â gured as pass-through logic for data transfer, reducing interconnect requirement. Our scheme not only reduces the overall length of global interconnects but also minimizes the power overhead without introducing any timing violations. Lastly, we present a register binding algorithm with the ob jective of register minimization. We have observed that not all pipelined FUs are operating at all time. Idle pipelined FUs can be used to store data temporarily, reducing stand-alone registers.
Low-Power Repeater Insertion for Global Interconnects
(2006-05-04) Peng, Yuantao; Xun Liu, Committee Chair; W. Rhett Davis, Committee Member; Gregory T. Byrd, Committee Member; Paul D Franzon, Committee Member
Repeater insertion is one of the most widely used techniques to reduce the signal propagation delay on global interconnects. The number of repeaters inserted into interconnects is expected to be enormous due to the ever-increasing chip dimension. The huge number of repeaters can take up significant silicon area and consume a lot of power. Consequently, minimization of power consumption of repeaters with timing closure constraints is a very important problem in future low-power VLSI design. In this dissertation, we investigate efficient schemes for low-power repeater insertion on global interconnects. We first analyze key issues on repeater library design by introducing an analytical low-power repeater insertion algorithm for uniform two-pin interconnects. Our study leads to the answer of how to design a compact repeater library for low-power in early design stages. We then discuss several low-power repeater insertion schemes under given timing constraints. These schemes achieve a better trade-off between solution quality and runtime than previously proposed approaches. To handle the signal integrity problem while performing repeater insertion, we next present a novel low-power repeater insertion scheme under both timing and signal slew rate constraints. The proposed scheme is able to capture both delay and slew rate information, resulting in high quality interconnect designs. Besides the repeater insertion algorithms for given interconnects, we also describe a simple yet effective power macromodel for global interconnects with the consideration of low-power repeater insertion. By incorporating the macromodel into a macrocell placement tool, we have achieved simultaneous minimization of timing violations and power dissipation.
A MIMO Receiver SOC for CDMA Applications
(2007-12-20) Chen, Tongtong; W. Rhett Davis, Committee Member; Paul D. Franzon, Committee Member; Xun Liu, Committee Chair
Multiple Input Multiple Output(MIMO) technique promises substantial increase of wireless channel capacity by using antenna arrays at both transmitters and receivers. It is one of the key technology to be used in the third generation wireless communication applications and is a current theme of international wireless research. Hardware implementation of MIMO receiver in today's wireless applications has stringent requirements such as high throughput, low power and high performance. This brings the difficulties to carry out the desired ASIC chip which is feasible to current silicon process. In this thesis, we introduce a new System-on-a-Chip(SoC) design for the 3G Code Division Multiple Access(3G-CDMA) MIMO receiver. The SoC chip consists of a space-time equalizer, a MIMO detector and a turbo decoder onto a single chip, which can be configured to handle different modulation schemes including QPSK and 16QAM according to the signal-to-noise ratio(SNR). At low SNR, QPSK modulation scheme can provide lower bit error rate(BER), while at high SNR, 16QAM scheme can have a larger throughput. Sphere decoding algorithm is used for MIMO detection to achieve near maximum likelihood (ML) performance with relatively lower complexity for practical silicon implementation. To improve the system performance further, we implement a turbo decode, which decode the transmitted information bits using the soft decision result from the sphere decoder. Our design can achieve much lower BER than other current MIMO ASICs in the low SNR range. The paper also analyze the trade-off between the hardware complexity and the BER performance of the MIMO receiver using MATLAB fixed-point simulation and hardware synthesis.
Rotary Clock based High-Frequency ASIC Design Methodology
(2007-11-01) Yu, Zhengtao; W. Rhett Davis, Committee Member; Alex Huang, Committee Member; Xun Liu, Committee Chair; Paul Ro, Committee Member
With the increase of operating frequencies and dimensions, modern VLSI chips consume substantial power dissipation. For synchronous circuit designs, the clock network is a major power consumer, often contributing more than 20\% of overall power consumption. Consequently, power-efficient clock distribution methods have been extensively researched. In particular, the rotary clock technique is one low-power clocking approach that utilizes the LC oscillating principle to reduce power consumption. However, there are several design challenges that prevent the application of rotary technique. In this dissertation, we have developed a software tool based on the method of partial element equivalent circuit (PEEC) that is capable of extracting the SPICE netlist from the layout specification of a rotary clock design. Using our tool, linked various design parameters of a rotary clock design to its oscillation frequency and power dissipation. We then propose a power minimization algorithm. Our algorithm derives a rotary clock structure that dissipates the minimal power while satisfying the clock dimension requirement and oscillating at the target frequency with the given clock load. We then developed a design methodology to implement the rotary clock based VLSI system. In particular, we present a circuit optimization scheme called skew spreading for rotary clock. Given an edge-triggered sequential circuit, skew spreading relocates the registers and derives the corresponding required clock arrival times, or skews, so that all skew values are distributed evenly in a preselected time window without changing the circuit functionality or the operating speed. We make the first attempt to design rotary based circuit by proposing a unified clock and circuit design methodology. Given a sequential circuit and a clock frequency, our scheme derives a rotary clock network and a functionally equivalent circuit so that they can be integrated to operate reliably at the target frequency. We have developed a physical design flow for rotary clock based design to address placement and timing issues. We have investigated the phase-locked-loop design under rotary clock technique. Our experiment results demonstrate that the charge-pump based PLL can be applied to to rotary clock network with 7% tuning range to cover the frequency deviation due to the process variations. Based on this design methodology, we have implemented a parallel transpose direct form 10-tap programmable FIR filter. Our experiment results show that in comparison with conventional clock tree based design we have achieved 12.8% total power savings and 34.6% clock tree network power savings without degrading the speed of circuits. In addition, the rotary clock based FIR filer has the peak current reduction of more than 40% with area degradation of less than 2% in comparison with clock tree based FIR filter design.