Browsing by Author "Xun Liu, Committee Member"

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Implementation of Double Precision Floating Point Arithmetic
(2007-03-08) Sudarsanam, Yasaswini; Xun Liu, Committee Member; Rhett Davis, Committee Member; Paul Franzon, Committee Chair
Floating Point Arithmetic is extensively used in the field of medical imaging, biometrics, motion capture and audio applications, including broadcast, conferencing, musical instruments and professional audio. Many of these applications need to solve sparse linear systems that use fair amounts of matrix multiplication. The objective of this thesis is to implement double precision floating point cores for addition and multiplication .These cores are targeted for Field Programmable Gate Arrays because FPGAs give the designer good control over the number of I/O pins and utilization of on chip memory. FPGAs are also comparable to floating point processors in their power consumption. The multiplier and adder cores conform to the IEEE 754 standard for double precision. The design is implemented on Xilinx ISE 8.2i and has been simulated on ModelSim 6.1i.The thesis pays significant attention to the analysis of the adder and multiplier cores in terms of pipelining and area so as to maximize throughput in any manner possible. It further throws light on variations of power with pipelining. Power measurements are done using XPower provided by ISE.
A Performance Analysis Framework for the Design of DSP Systems
(2008-04-15) Hourani, Ramsey Salim; Zhilin Li, Committee Member; Xun Liu, Committee Member; W. Rhett Davis, Committee Co-Chair; William Edmonson, Committee Member; Winser E. Alexander, Committee Chair
A Testbed for Technology Characterization
(2009-12-08) Iles, Philip Michael; W. Rhett Davis, Committee Chair; Paul Franzon, Committee Member; Xun Liu, Committee Member
As feature sizes continue to decrease, fundamental properties of MOSFET devices begin to hinder the performance gains from one generation to another. The advent of the Tunneling Field Effect Transistor (TFET) provides hope for continued reduction in feature size whilst solving some of the scaling issues such as leakage current. The purpose of this work is to discuss key metrics that help to quantify the improvements among technology nodes, specifically a comparison between TFETs and traditional MOSFETs. Test structures that allow for the measurement of on and off current, device speed, variation as it relates to on current and threshold voltage, as well as SRAM yield and bitcell read and write noise margins are discussed. In addition, a slight modification to a rapid characterization test structure used to measure threshold variation is proven to help reduce leakage seen within the test structure. Lastly, the structures are actually fabricated in a 90nm bulk and a 45nm SOI process and measurements from the 90nm bulk process are presented.
Transaction-level Modeling for a Network-on-chip Router in Multiprocessor System
(2009-08-10) Hu, Jianchen; William Rhett Davis, Committee Chair; Gregory T. Byrd, Committee Member; Xun Liu, Committee Member
As the complexity of SoC design grows, the traditional register transfer level (RTL) centric design flow cannot meet the time to market. In that case, a higher modeling level of abstraction is need for designer to explore the design space at system level. Transaction-level model (TLM) is such an approach since it could run much faster than RTL model and also have enough accuracy. There are different modeling styles of TLM for different applications. In this thesis, we develop a hybrid-TLM of Network-on-chip (NoC) based on OSCI TLM-2.0 standard. We use a simplified version of the AMBA AXI protocol for the bus. This model contains a cycle-accurate AXI router and other periphery modules with approximately-timed coding style, which achieve fast simulation speed and accurate result. This model keeps good interoperability since it entirely based on TLM-2.0 standard. And the designer could build complex NoCs by making use of this model.