Adding Scalability to IBIS by Using AMS Languages
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2006-05-04
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Abstract
From 1993 to about 1998, IBIS remained THE digital IO buffer model format. But as the operating frequencies & complexity of I/O buffers increased, IBIS has been left behind in favor of SPICE models, since IBIS is inaccurate or unable to model these advanced buffers. This trend brings the industry back toward a single EDA vendor solution, which is what IBIS was designed to prevent. In an effort to relinquish these shortcomings, multi-lingual model extensions were added to IBIS Version 4.1. Specifically: Berkeley-SPICE, VHDL-AMS and Verilog-AMS files.
These extensions in IBIS 4.1 give IBIS practically unlimited behavioral and structural modeling capabilities as well as more accuracy. The problem is that the AMS languages have been slow in making their way into SI tools and the SI community; mainly due to the associated learning curve, since AMS is relatively new to the SI world.
The solution was to build an AMS library of tool independent basic elements ('element library') and a separate 'template library' which would contain the models of complex buffers (Pre-emphasis, LVDS, DDR2 etc). The templates would be created by instancing elements from the 'element library'. An IBIS to AMS converter would convert conventional IBIS files into AMS format and provide the data for the template. The IBIS macro-modeling committee was created in July 2005 with these main goals in mind.
This thesis deals with the new AMS macro-modeling methodology put forth by the IBIS macro-modeling committee and the contributions I made to it as its only student member. My specific contribution was the IBIS to AMS (ibis2ams) converter tool. The thesis also presents the updates I made to the IBIS plotting utility (s2iplt) and the spice to IBIS toolkit (s2ibis). All tools are publicly available on the NCSU ERL website.
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VHDL, Verilog, Signal Integrity, IBIS, SI, Verilog-AMS, VHDL-AMS, AMS, Electrical Engineering, IBIS-AMS
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Degree
MS
Discipline
Computer Engineering
