Characterization of Context Switch Effects on L2 Cache

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Date

2007-04-16

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Abstract

Multitasking is common in most systems. In order to use the processor resources efficiently, a multitasking system schedules processes to run for certain intervals by switching (saving and restoring) their contexts. However, since processes bring their own data to the cache when they are running, context switching causes each process to suffer from more misses. Behavior of L2 cache misses due to context switches with different cache configurations, working-set sizes, and process priorities is not well-understood. Analysis of this behavior will give insights about the reasons and ways to mitigate these misses. The first contribution of this paper is the characterization of the context switch effect on L2 cache relating to the process priorities. The paper also characterizes the context switch effect with various cache configurations, including the size and associativity of the cache. Finally, it defines two types of misses that occur due to context switches.Replacement context switch misses occur when a process' working set is replaced by an interfering process. Reorder context switch misses occur due to reordering of lines by an interfering process, i.e. moving lines from more recently used to less recently used position. Based on the characterization results, we found that the number of context switch misses increases with lower priorities. On average, a process with the lowest priority suffers 15.4 times more L2 cache misses due to the context switch effect than the case there is no time-sharing, while the process with the highest priority suffers only 1.2 times more misses. We also observed that the impact of context switch is affected more by the priority of the process itself, rather than the priority of the interfering process. We also found that increase in associativity increases reorder context switch misses. Finally, the highest number of context switch misses occur when the size of a process' working set is close to the cache size.

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Keywords

Cache memories, context switch, multiprogramming, scheduling priority

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Degree

MS

Discipline

Computer Engineering

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