Power Analysis and Instruction Scheduling for Reduced di/dt in the Execution Core of High-Performance Microprocessors
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1999-06-29
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Power dissipation is becoming a first-order design issue in high-performance microprocessors as clock speeds and transistor densitiescontinue to increase. As power dissipation levels rise, thecooling and reliability of high-performance processors becomesa major issue. This implies that significant research needsto be done in the area of architectural techniques for reducingpower dissipation.One major contributor to a processor's average peak powerdissipation is the presence of high di/dt in its executioncore. High-energy instructions scheduled together in a singlecycle can result in large current spikes during execution. Inthe presence of heavily weighted regions of code, these currentspikes can cause increases in the processor's average peakpower dissipation. However, if the compiler produces largeenough regions, a certain amount of schedule slack should exist,providing opportunities for scheduling optimizations based onper-cycle energy constraints.This thesis proposes a novel approach to instruction schedulingbased on the concept of schedule slack, which builds energyefficient schedules by limiting the energy dissipated in asingle cycle. In this manner, a more uniform di/dt curve isgenerated resulting in a decrease in the execution core's averagepeak power dissipation.
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MS
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Computer Engineering
