Power Analysis and Instruction Scheduling for Reduced di/dt in the Execution Core of High-Performance Microprocessors

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dc.contributor.advisor Dr. Thomas M. Conte, Chair en_US
dc.contributor.advisor Dr. Wentai Liu, Member en_US
dc.contributor.advisor Dr. Alex Eichenberger, Member en_US
dc.contributor.author Toburen, Mark C en_US
dc.date.accessioned 2010-04-02T18:03:51Z
dc.date.available 2010-04-02T18:03:51Z
dc.date.issued 1999-06-29 en_US
dc.identifier.other etd-19990628-171119 en_US
dc.identifier.uri http://www.lib.ncsu.edu/resolver/1840.16/1425
dc.description.abstract Power dissipation is becoming a first-order design issue in high-performance microprocessors as clock speeds and transistor densitiescontinue to increase. As power dissipation levels rise, thecooling and reliability of high-performance processors becomesa major issue. This implies that significant research needsto be done in the area of architectural techniques for reducingpower dissipation.One major contributor to a processor's average peak powerdissipation is the presence of high di/dt in its executioncore. High-energy instructions scheduled together in a singlecycle can result in large current spikes during execution. Inthe presence of heavily weighted regions of code, these currentspikes can cause increases in the processor's average peakpower dissipation. However, if the compiler produces largeenough regions, a certain amount of schedule slack should exist,providing opportunities for scheduling optimizations based onper-cycle energy constraints.This thesis proposes a novel approach to instruction schedulingbased on the concept of schedule slack, which builds energyefficient schedules by limiting the energy dissipated in asingle cycle. In this manner, a more uniform di/dt curve isgenerated resulting in a decrease in the execution core's averagepeak power dissipation. en_US
dc.rights I hereby certify that, if appropriate, I have obtained and attached hereto a written permission statement from the owner(s) of each third party copyrighted matter to be included in my thesis, dissertation, or project report, allowing distribution as specified below. I certify that the version I submitted is the same as that approved by my advisory committee. I hereby grant to NC State University or its agents the non-exclusive license to archive and make accessible, under the conditions specified below, my thesis, dissertation, or project report in whole or in part in all forms of media, now or hereafter known. I retain all other ownership rights to the copyright of the thesis, dissertation or project report. I also retain the right to use in future works (such as articles or books) all or part of this thesis, dissertation, or project report. en_US
dc.title Power Analysis and Instruction Scheduling for Reduced di/dt in the Execution Core of High-Performance Microprocessors en_US
dc.degree.name MS en_US
dc.degree.level Master's Thesis en_US
dc.degree.discipline Computer Engineering en_US


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