A Synthesizable HDL Model for Out-of-Order Superscalar Processors.
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Date
2009-08-10
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Abstract
Many contemporary servers, personal and laptop computers, and even cell phones are powered by high-performance superscalar processors. In the past, conventional microarchitecture and technology scaling has afforded leaps in their performance and functionality. Today, conventional microarchitecture and technology scaling are both yielding lower returns with increasing costs. Therefore, any microarchitecture level decision to increase performance needs to be critically analyzed from a technology standpoint. To address this critical need, we have developed a register transfer level (RTL) model of a superscalar microarchitecture with similar complexity of a current generation processor. The RTL model is written in Verilog and is fully synthesizable. The model can be implemented in different technology nodes using a well established ASIC design flow to provide high fidelity estimation of propagation delay, power consumption, area, and other technology related costs. The RTL model is supplemented with a register file compiler to estimate the costs of multi-ported memory structures which are extensively used in a superscalar microarchitecture. The RTL model is also tightly integrated with a C++ functional simulator to assist and accelerate verification.
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Microarchitecture, Verilog, Superscalar
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Degree
MS
Discipline
Computer Engineering
