Memory Predecryption: Hiding the Latency Overhead of Memory Encryption

Show full item record

Title: Memory Predecryption: Hiding the Latency Overhead of Memory Encryption
Author: Rogers, Brian Michael
Advisors: Jun Xu, Committee Member
Yan Solihin, Committee Chair
Gregory Byrd, Committee Member
Abstract: Security has emerged as an important area in the field of computer research today. With the emergence of hardware-based attacks, research has been done not only on software solutions to security, but also on providing security with the help of architectural support. More specifically, hardware encryption and authentication of off-chip memory have recently been studied as ways to ensure that malicious agents cannot see data in its plaintext form or tamper with data in an undetected manner during an application's execution. When used in combination, encryption and authentication can help to provide a secure processing environment. While various techniques have been proposed for performing memory encryption in a secure processor, current schemes suffer from extra performance and storage overheads. This paper presents predecryption as a method of providing this encryption with less overhead. This is accomplished by using well-known prefetching techniques to retrieve data from memory and perform decryption before it is needed by the processor on latency-critical read operations. Our results, tested mostly on SPEC 2000 and NAS benchmarks, show that using this predecryption scheme can actually result in no increase in execution time over a system with no encryption, despite an extra 128 cycle decryption latency per memory block access.
Date: 2005-04-22
Degree: MS
Discipline: Computer Engineering

Files in this item

Files Size Format View
etd.pdf 260.3Kb PDF View/Open

This item appears in the following Collection(s)

Show full item record