Development of ASIC Technology Library for the TSMC 0.25 micrometers Standard Cell Library

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Title: Development of ASIC Technology Library for the TSMC 0.25 micrometers Standard Cell Library
Author: Sundararaman, Vishwanath
Advisors: Dr. Griff Bilbro, Committee Member
Dr. Eric Rotenberg, Committee Member
Dr. Paul D. Franzon, Committee Chair
Abstract: The Synopsys synthesis tool generates the hierarchical netlist of a design using worst-case and best-case ASIC technology libraries. The worst-case library checks for the setup time violation and the best-case library checks for the hold time violations of the design. The worst-case library is characterized by a supply voltage of 2.25V, operating temperature of 125°C, and slow process corner. The best-case library is characterized by a supply voltage of 2.75V, operating temperature of -55°C, and fast process corner. The technology libraries are developed for the CMOS TSMC 0.25μm technology. The CMOS nonlinear delay models are used for delay calculations. Variations in operating temperature, supply voltage and manufacturing process causes performance variations in electronic networks. Using different operating conditions, the timing of the design under different environmental conditions can be evaluated. The delay values specified in the cells for a technology specify a set of nominal operating condition. The worst-case and best-case libraries are developed by running HSPICE simulations for all the 36 basic cells. The technology library contains information used for the following synthesis activities: • Translation — functional information for each cell • Optimization — area and timing information for each cell (including timing constraints on sequential cells) • Design rule fixing — design rule constraints on cells
Date: 2003-08-19
Degree: MS
Discipline: Computer Engineering
URI: http://www.lib.ncsu.edu/resolver/1840.16/1629


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