High-Speed Transceiver Design in CMOS using Multi-level (4-PAM) Signaling

Show full item record

Title: High-Speed Transceiver Design in CMOS using Multi-level (4-PAM) Signaling
Author: Joseph, Balu
Advisors: Dr. Gianluca Lazzi, Committee Member
Dr. Wentai Liu, Committee Chair
Dr. Rhett Davis, Committee Member
Abstract: The design of a 4 Gbps serial link transceiver in 0.35μm CMOS process is presented. The major factors limiting the performance of high-speed links are transmission channel bandwidth, timing uncertainty and on-chip frequency limitations. The design uses a combination of multi-level signaling (4-PAM) and transmit pre-emphasis to overcome the channel low-pass characteristics. High on-chip frequency signals are avoided by multiplexing and de-multiplexing the data directly at the pads. Timing recovery is done through over-sampling the data using multi-phase clocks generated from a low-jitter PLL. The design achieves a 4 Gbps data transmission rate, with a transmit data jitter of 53.2 ps (p-p), while consuming 879.4 mW of power from a 3.3 V supply.
Date: 2003-04-22
Degree: MS
Discipline: Electrical Engineering
URI: http://www.lib.ncsu.edu/resolver/1840.16/186

Files in this item

Files Size Format View
etd.pdf 5.140Mb PDF View/Open

This item appears in the following Collection(s)

Show full item record