High-Speed Transceiver Design in CMOS using Multi-level (4-PAM) Signaling

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Date

2003-04-22

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Abstract

The design of a 4 Gbps serial link transceiver in 0.35μm CMOS process is presented. The major factors limiting the performance of high-speed links are transmission channel bandwidth, timing uncertainty and on-chip frequency limitations. The design uses a combination of multi-level signaling (4-PAM) and transmit pre-emphasis to overcome the channel low-pass characteristics. High on-chip frequency signals are avoided by multiplexing and de-multiplexing the data directly at the pads. Timing recovery is done through over-sampling the data using multi-phase clocks generated from a low-jitter PLL. The design achieves a 4 Gbps data transmission rate, with a transmit data jitter of 53.2 ps (p-p), while consuming 879.4 mW of power from a 3.3 V supply.

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Keywords

high-speed transceiver, equalization, CDR, serial-link, SERDES, multi-level, 4-PAM

Citation

Degree

MS

Discipline

Electrical Engineering

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