Efficiently Adding Secure Communications to Networked Low-End Embedded Systems using Software Thread Integration

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Title: Efficiently Adding Secure Communications to Networked Low-End Embedded Systems using Software Thread Integration
Author: Ganesan, Prasanth
Advisors: Dr. Alexander Dean, Committee Chair
Dr. Gregory Byrd, Committee Member
Dr. Mihail Sichitiu, Committee Member
Abstract: The wide spread acceptance of distributed embedded networks is motivated by factors such as cost, weight and power consumption. Communication protocols or MAC layer protocols can be implemented in software on microcontrollers to save costs in comparison to dedicated chips. Traditional methods for implementing a protocol's lowest layers (sending and receiving bits and bytes) in software incur significant execution time overhead, which limits system efficiency and peak performance, increasing power consumption. An additional constraint on communication is security. Wireless networks in particular require secure channels of communication due to the open nature of the RF medium, which makes them vulnerable to attacks. To provide privacy these networks use security protocols. Cryptographic support is a vital ingredient of these protocols. All data transmitted and received is encrypted or decrypted in real time. This further burdens the system processor, forcing lower network bit-rates or higher processor clock speeds and therefore increasing power consumption. Software Thread Integration (STI) is a software technique which interleaves multiple threads at the machine instruction level. This enables system resources to be used efficiently and eliminates context switch overhead. This technique gives a wonderful opportunity to utilize the free cycles generated in communication protocols by cryptographic algorithms. Real-time work is performed faster, allowing for better throughput rates. Throughput increase is also attained because of more efficient use of the communication channel. Timing constraints of the communication threads are met while cryptographic duties are performed concurrently. This saves many processor cycles as well. In some cases it may also allow hardware to software migration without any effect on the throughput rates. This thesis proposes a set of methods to add cryptographic support efficiently to networked embedded systems using STI and save processor cycles and power. A system level software architecture is proposed to enable the use of integrated threads efficiently. TDMA threads are integrated with encryption/decryption threads and, using the above technique and proposed architecture, implemented as part of an open source operating system AVRX. The results show that an STI based implementation is more efficient in the case of synchronous transmission compared to traditional ISR or busy-wait schemes. Our analysis of an integrated thread including the RC4 stream cipher at a relative bus speed of f[subscript cpu]/16 showed a 22% increase in algorithm throughput while data throughput increased by 23%. Further results and benefits are tabulated and evaluated.
Date: 2003-08-31
Degree: MS
Discipline: Computer Engineering
URI: http://www.lib.ncsu.edu/resolver/1840.16/2096

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